EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 1Lecture 20Analog-to-Digital Converters (continued)– Comparator design (continued)• Comparator architecture examples– Techniques to reduce flash ADC complexity• Interpolating• Folding• Interpolating & folding– Residue Type ADCs• Two-Step flash• Pipelined ADCs– Architecture basics– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall ADC performanceEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 2CMOS Comparator ExampleFlash ADCRef: A. Yukawa, “A CMOS 8-bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9• Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (Vref=3.8V, LSB~15mV)• No offset cancellationPreamp. LatchEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 3Comparator with Auto-ZeroRef: I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.Note: Reference & input both differentialEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 4Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.Voffset CCRe f Re fOffsetVVVVVFlash ADCComparator with Auto-ZeroEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 5Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.VoffsetVo Offseto P1 P2In In C CCCRe f Re fo P1 P2In InVV A AV V V VSubstituting for from previous cycle:VVVVV A AVVNote: Offset is cancelled & difference betweeninput & reference established Flash ADCComparator with Auto-ZeroEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 6Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.Flash ADCUsing Comparator with Auto-ZeroEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 7Auto-Zero ImplementationRef:I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC March 2000, pp. 318-25EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 8Comparator ExampleRef: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995• Variation on Yukawa latch used w/o preamp• Good for low resolution ADCs (in this case 1.5bit/stage for a pipeline we will see later are tolerant of high offset) • Note: M1, M2, M11, M12 operate in triode mode• M11 & M12 added to vary comparator threshold• Conductance at node X is sum of GM1& GM11xEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 9Comparator Example (continued)Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995Vo1G1G2 CoxV V V VGWWI1 th R th11 11LCoxV V V VGWWI2 th R th21 11LWCW11ox 1V V V VGI1 I2 R RWL1 Vo1 Vo2 • M1, M2, M11, M12 operate in triode mode with all having equal L• Conductance of input devices:• To 1st order, for W1= W2 & W11=W12Vthlatch= W11/W1 x VRwhere VR= VR+- VR- VRfixed W11, 12 varied from comparator to comparator Eliminates need for resistive dividerEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 10Comparator Example• Used in a pipelined ADC with digital correctionNo offset cancellation requiredDifferential reference & input• M7, M8 operate in triode region• Preamp gain ~10• Input buffers suppress kick-back• f1high Cscharged to VR & f2Bis also high current diverted to latchcomparator output in hold mode• f2high Csconnected to S/Hout & comparator input (VR-S/Hout), current sent to preamp comparator in amplify modeRef: S. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC , NO. 6, Dec. 1987EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 11Bipolar Comparator Example• Used in 8bit 400Ms/s & 6bit 2Gb/s flash ADC • Signal amplification during f1 high, latch operates when f1 low• Input buffers suppress kick-back & input current• Separate ground and supply buses for front-end preamp kick-back noise reductionRef: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXX, pp. 98 - 99, February 1987Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXXI, pp. 232 - 233, February 1988PreampLatched ComparatorEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 12Reducing Flash ADC ComplexityE.g. 10-bit “straight” flash– Input range: 0 … 1V– LSB = : ~ 1mV – Comparators: 1023 with offset < 1/2 LSB– Assuming Cin for each comparator is 0.1pF & power 3mW• Total input capacitance: 1023 * 100fF = 102pF• Power: 1023 * 3mW = 3W High power dissipation & large area & high input cap.Techniques to reduce complexity & power dissipation :– Interpolation– Folding– Folding & Interpolation– Two-step, pipeliningEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 13Interpolation• Idea– Reduce number of preamps & instead interpolate between preamp outputs• Reduced number of preamps– Reduced input capacitance– Reduced area, power dissipation• Same number of latches (2B-1)• Important “side-benefit” – Decreased sensitivity to preamp offset Improved DNLEECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs © 2010 Page 14Flash
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