EE247 Lecture 7 Summary last lecture Automatic on chip filter tuning continued from last lecture Continuous tuning Reference integrator locked to a reference frequency DC tuning of resistive timing element Periodic digitally assisted tuning Systems where filter is followed by ADC DSP existing hardware can be used to periodically update filter freq response Continuous time filters Bandpass filters Example Gm C BP filter using simple diff pair Linearity noise issues Various Gm C Filter implementations Comparison of continuous time filter topologies EECS 247 Lecture 7 Filters 2005 H K Page 1 Summary last lecture Continuous time filters Opamp MOSFET C filters Opamp MOSFET RC filters Gm C filters Frequency tuning for continuous time filters Trimming via fuses Automatic on chip filter tuning Continuous tuning Utilizing VCF built with replica integrators Use of VCO built with replica integrators EECS 247 Lecture 7 Filters 2005 H K Page 2 Master Slave Frequency Tuning Reference Integrator Locked to Reference Frequency Replica of main filter Gm C Vin I Gm Vref Gm C Vref Vout Vtune Replica of main filter integrator e g Gm C building block used Utilizes the fact that a DC voltage source connected to the input of the Gm cell generates a constant current proportional to the transconductance and the voltage reference I Gm Vref EECS 247 Lecture 7 Filters 2005 H K Page 3 Reference Integrator Locked to Reference Frequency Consider the following sequence Integrating capacitor is fully discharged t 0 At t 0 the integrator input is connected to the output of the Gm cell then Vin I Gm Vref Gm Vout Vref C1 Vtune VC1 T t 0 EECS 247 Lecture 7 Filters VC1 Gm Vref T C1 time 2005 H K Page 4 Reference Integrator Locked to Reference Frequency Since at the end if the period T VC1 G m Vref T I Gm Vref Vin C1 Gm Vout Vref C If VC1 is forced to be equal to Vref then Vtune VC1 C T N Gm fclk VC1 G m Vref T T C1 time t 0 How do we manage to force VC1 Vref Use feedback EECS 247 Lecture 7 Filters 2005 H K Page 5 Reference Integrator Locked to Reference Frequency Replica of main filter Gm S2 Vref S3 A Gm C1 S1 C2 Three clock phase operation To analyze study one phase at a time Ref A Durham J Hughes and W Redman White Circuit Architectures for High Linearity Monolithic Continuous Time Filtering IEEE Transactions on Circuits and Systems pp 651 657 Sept 1992 EECS 247 Lecture 7 Filters 2005 H K Page 6 Reference Integrator Locked to Reference Frequency P1 high S1 closed S2 Vref S3 A Gm S1 C1 C2 C1 discharged C2 retains its previous charge EECS 247 Lecture 7 Filters 2005 H K Page 7 Reference Integrator Locked to Reference Frequency P2 high S2 closed S2 Vref S3 A Gm I Gm Vref C1 C2 C1 charged with constant current I Gm Vref C2 retains its previous charge P2 VC1 G m Vref T 2 C1 VC1 T1 T2 EECS 247 Lecture 7 Filters 2005 H K Page 8 Reference Integrator Locked to Reference Frequency P3 high S3 closed S2 S3 A Gm Vref C1 T1 C2 C1 charge shares with C2 Few cycles following startup Feedback forces C1 Gm to assume T2 VC1 VC2 V r e f s i n c e VC1 Gm Vref T 2 C1 t h e n Vref Gm Vr e f T 2 or C1 Gm C1 T 2 N fclk EECS 247 Lecture 7 Filters 2005 H K Page 9 Summary Reference Integrator Locked to Reference Frequency S2 Vref S3 A Gm C1 C2 To Main Filter Integrator time constant locked to an accurate frequency Tuning signal used to adjust the time constant of the main filter integrators EECS 247 Lecture 7 Filters Feedback forces Gm to vary so that i n t g C1 Gm N fclk or 0i n t g Gm C1 fclk N 2005 H K Page 10 Issues Reference Integrator Locked to Reference Frequency Problems to be aware of S2 Vref S3 A Gm C1 C2 To Main Filter 0i n t g Gm C1 fclk N Tuning error due to master integrator DC offset EECS 247 Lecture 7 Filters 2005 H K Page 11 Issues Reference Integrator Locked to Reference Frequency What is DC offset Vo Simple example Vos For the differential pair shown here any mismatch in input device characteristics would cause DC offset Vo 0 requires a non zero input voltage Vin M1 M2 Offset could be modeled as a small DC voltage source at the input Example Differential Pair EECS 247 Lecture 7 Filters 2005 H K Page 12 Gm Cell Offset Induced Error Voltage source representing DC offset Vos S2 S3 A Gm Vref C1 I Gm Vref Vos C2 Effect of Gm cell DC offset VC1 VC2 Vref Ideal VC1 Gm Vr e f T 2 C1 w i t h o f f s e t VC1 Gm Vref Vos T 2 C1 V C1 or T 2 1 o s Gm V ref EECS 247 Lecture 7 Filters 2005 H K Page 13 Gm Cell Offset Induced Error Vos S2 S3 A Gm Vref I Gm Vref Vos C1 C2 Example V T 2 1 o s Gm V ref V f o r os 1 1 0 Vref C1 10 error i n tuning EECS 247 Lecture 7 Filters 2005 H K Page 14 Issues Gm Cell Offset Induced Error Assume differential integrator Add a pair of auxiliary inputs to the input stage for offset cancellation purposes Cint g Vo Vinaux M3 Aux Main Input Input M4 M1 M2 Vinmain EECS 247 Lecture 7 Filters 2005 H K Page 15 Reference Integrator Locked to Reference Frequency Offset Cancellation Incorporated P2 Vref 2 P2B P3 C3a Vcm Vref 2 P2B C3b P2 P3 P2 P1 C1 C2 P1 P2 P3 P3 Vtune Gm cell two sets of input pairs Aux input pair C3a b Offset cancellation Same clock timing EECS 247 Lecture 7 Filters 2005 H K Page 16 Reference Integrator Locked to Reference Frequency P3 High Update Store offset Vref 2 C3a Vo s Vcm Vref 2 C1 C2 Vout Vo s C3b Vtune Gm cell Unity gain configuration via aux inputs C3a b Store Gm cell offset C1 C2 Charge sharing EECS 247 Lecture 7 Filters 2005 H K Page 17 Reference Integrator During Offset Cancellation Phase Gm cell Unity gain configuration via aux inputs main input shorted C3a Vo s Vcm Vout Vo s C3a b acquire charge equal to Vos Store Gm cell offset Vout Vo s C3b VC3a b Vo s C3a Vcm Note This technique can be used in various other applications EECS 247 Lecture 7 Filters Vout Vo s C3b 2005 H K Page 18 Reference Integrator Locked to Reference Frequency P1 High Reset VC3a b Vos C3a Vref 2 Vo s Vcm Vref 2 C1 C2 C3b Vtune Gm cell Reset C1 Discharge C2 Hold Charge C3a b Hold Charge Offset stored on C3a b cancels gm cell offset EECS 247 Lecture 7 Filters 2005 H K Page …
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