UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering And Computer Sciences MULTIFREQUENCY CELL IMPEDENCE MEASUREMENT EE247 Term Project Eddie Ng Mounir Bohsali Professor Bernhard BoserIntroduction: The main objective of this project is to build a system capable of measuring cell impedance which can be modeled as a parallel RC equivalent network. In order to alleviate the required precision, the channel/cell block is configured in a feedback network whose output signal is compared to the calibrated reference signal. The resulting cell impedance value is passed through ten pairs of I/Q mixers in parallel. After the signal is low pass filtered, it is digitized and fed into a DSP to calculate the end result. Since calibration is done in an early stage in the system, only the first amplifier with the channel/cell feedback configuration requires high precision (0.01%). The simulated system shows that the final results are accurate within 0.01% after modeling the critical non-idealities of all different blocks such as equivalent input referred and quantization noise, finite open loop gain, finite amplifier bandwidth, DC offset, INL, and DNL. Hierarchical Design Description: Fig. 1 shows a block level simulation diagram of the entire system. To first order, the system was initially simulated with ideal components. As a second step, critical non-idealities of each building block based on actual commercial products were added, and the system was re-simulated and the results were verified to meet the specs. Feedback amplifier: The channel/cell is placed in a negative feedback configuration around the amplifier. The resulting transfer function is Cchannel)(CcellRfsRchannelRcellRfZcellRfH(s)_ideal +⋅⋅−+−=−= where Cchannel)(CcellRchannel)(Rcells1RchannelRcellZcell+⋅+⋅++= Refer to Figures 4 and 5 for Simulink block level implementations for the above two transfer functions. In order to measure the cell impedance, ten input sine waves at logarithmically spaced frequencies (f1, f2, … f10) with amplitudes as shown in table 1 are applied to the channel containing both the cell and the solution (See Fig. 3). The input amplitudes are chosen as such to prevent output saturation. In that order, the table below (Table 1) showing minimum and maximum gains at each frequency was generated. The supply voltage (+/-15V) of the chosen commercial op-amp sets a upper limit on the input voltage given by Vcc],gain_maxVsupply[min Vin_max ≤ The integrated output noise sets a lower limit on the input voltage. Since ten sine waves are applied simultaneously to the amplifier, each signal amplitude could add up in phase. In order to prevent saturation, an “n factor” is used to scale each input. Simulation showed that an n factor of 8 is sufficient to limit the output swing to +/- 12.5V (maximum output voltage swing of commercial amplifier used in the design).Frequency Minimum Gain (Cch=50pF, Rch=250Ω) Maximum Gain (Cch=1nF, Rch=500Ω) Maximum Input Amplitude Vo-p 100KHz 0.200025 0.4049 12.5 / n 2.15KHz 0.200114 0.422173 12.5 / n 4.64KHz 0.20053 0.494883 12.5 / n 1MHz 0.20245 0.74457 12.5 / n 2.15MHz 0.211087 1.408205 8.9 / n 4.64MHz 0.247442 2.941246 4.2 / n 10MHz 0.372285 6.292726 2.0 / n 21.5MHz 0.704102 13.50792 0.93 / n 46.4MHz 1.470623 29.14195 0.43 / n 100MHz 3.146363 62.80127 0.2 / n Table 1. Summary of maximum input amplitudes allowed before output clipping. Simulation suggest usage of n=8, To further refine the model, non-idealities such as finite open-loop gain, offset, finite bandwidth, input-referred noise are added to the Simulink models. Finite open loop gain: The finite open loop gain results in a gain error in the above ideal transfer function as follows: )ZRf(1a111H(s)_idealH(s)++⋅= , where a = finite amplifier gain Refer to Figure 5 for a Simulink implementation of the above transfer function. Finite amplifier bandwidth: The finite amplifier bandwidth is modeled as follows: dBwjwoaoa3_1+= where ao = low frequency gain DC offset and input referred noise: DC offset is modeled in Simulink as a constant block, and input referred noise is modeled using a random signal generator. The THS4021 op-amp from TI, inc. with specifications that meet the above constraints is used in the design The following are the key specs of the above op-amp: Vsupply: +/-15V Output voltage range: +/- 12.5V Input voltage range: +/- 15V Open loop gain: 60V/mV Vos: 0.5mV Gain Bandwidth: 350MHz Input referred noise: 1.5nV/sqrt(Hz)Calibration: Calibration is performed in an early stage of the system. A dedicated path for calibration containing a channel without cells is placed in parallel with the path containing channel with cells. A differential topology is used to subtract the measured analog voltage signal from the calibrated channel only analog voltage signal. This is done directly after the first stage analog amplifier. The transfer function of the resulting network is: Zcell)channelZchannel(ZZcellRf-H(s)+⋅= Since calibration is being done in an early stage of the system, all the analog components following the fist stage amplifier only need to carry approximately a 1% accuracy. Refer to Figures 7 and 8 for measurement calibrated values of Rchannel and Cchannel. Mixers: In order to separate the outputs at the different frequencies of interest, the signal is fed into twenty analog mixers separated into ten pairs. Each pair is tuned to one input frequency (i.e. f1, f2, … ,f10). Within each pair of mixers, the two local oscillator frequencies are 90o out of phase producing the real and the imaginary parts of the output signal. The commercial AD831 mixer from Analog Devices is used in this system. The mixer specifications as summarized as follows: Vsupply = +/-5V 1dB compression point = 10dBm IP3 = 24dBm LO drive = -10dBm Bandwidth = 500MHz for both RF and LO SSB NF = 10.3dB The mixers are implemented in Simulink. Since the NF of the mixer is critical in this application, it is modeled in Simulink as a random signal generator added with the input of the mixer. Low Pass Filters: Following the mixers, low pass filters are used to attenuate the high frequency unwanted signals that result from the mixing operation and keeping only the DC signal of interest. In Simulink, the low pass filters are implemented as a sixth order Bessel low pass filters with fpass=1/10 of input frequency. We
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