1948 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998A 10-b, 500-MSample/s CMOS DAC in 0.6 mmChi-Hung Lin and Klaas BultAbstract— A 10-b current steering CMOS digital-to-analogconverter (DAC) is described, with optimized performance forfrequency domain applications. For sampling frequencies up to200 MSample/s, the spurious free dynamic range (SFDR) isbetter than 60 dB for signals from dc to Nyquist. For samplingfrequencies up to 400 MSample/s, the SFDR is better than 55 dBfor signals from dc to Nyquist.The measured differential nonlinearity and integral nonlinear-ity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively.The circuit is fabricated in a 0.35-m, single-poly, four-metal, 3.3-V, standard digital CMOS process and occupies 0.6 mm2. Whenoperating at 500 MSample/s, it dissipates 125 mW from a 3.3-Vpower supply. This DAC is optimized for embedded applicationswith large amounts of digital circuitry.Index Terms—CMOS analog integrated circuits, digital–analogconversion, matching, mixed analog–digital integrated circuits.I. INTRODUCTIONTHE pressure to reduce cost in mass market communi-cation devices such as cable modems and digital cableset-top boxes has created a need for embedded high-speedhigh-resolution digital-to-analog converters (DAC’s). With theability to integrate analog circuits with memory and digitalsignal processing (DSP) circuits on the same die, CMOS tech-nology is poised to meet that challenge. In the past 20 years,much research has been devoted to DAC’s [1]–[8] optimizedfor time domain applications, such as high-resolution displaysfor computer graphics and high definition television (HDTV).These DAC’s were mainly focused on dc linearity, settlingbehavior, and glitch energy performance. When used to syn-thesize sinewaves in frequency-domain applications, however,their spurious free dynamic range (SFDR) performance istypically not sufficient for broad-band applications.As an example, a simplified architecture of a cable modemheadend transmitter is shown in Fig. 1. The cable modemsystem consists of multiple channels, where each channel con-tains a digital modulator and a DAC. The channels can havedifferent digital modulation schemes, for example, quadratureamplitude modulation (QAM) or quadrature phase-shift keying(QPSK). Without a high-speed, high-resolution DAC, thesemodulation functions must be implemented in the analogdomain, which generally results in relatively poor qualitysignals.When multiple channels are combined simultaneously, it isvery important that the DAC’s meet a minimum SFDR, orsignals in one channel will be corrupted by spurious com-Manuscript received June 25, 1998; revised August 19, 1998.The authors are with the Broadcom Corporation, Irvine, CA 92618 USA(e-mail: [email protected], [email protected]).Publisher Item Identifier S 0018-9200(98)08566-7.ponents from other channels. Therefore, the major challengefor designing DAC’s for frequency domain applications is toobtain large wideband SFDR. Fig. 2 shows an example of a16-QAM spectrum for cable modem upstream signals. Thetransmitted signal frequencies range from 5–65 MHz. Thespecification of the multimedia cable network system (MCNS)requires the (aliased) harmonics to be at least 47 dB below thefundamental signal. Experimental results have shown that thisnumber translates into an SFDR of more than 52 dB for asingle tone sinewave. That is a difficult requirement to meetfor DAC’s operating at high signal frequencies.The goal of the DAC reported here is to obtain true 10-bitperformance (SFDR60 dB) for signals from dc to Nyquist,for sampling speeds up to 200 MSample/s. For embeddedapplications, use of standard digital CMOS processes and asmall chip area is a must. The chip area of this DAC is 0.6mmin a 0.35 m, single-poly, four-metal, 3.3 V, standarddigital CMOS process.Sections II and III discuss the advantages and shortcomingsof binary-weighted DAC’s and thermometer-coded DAC’s, re-spectively. Section IV compares the area requirement for thesebinary-weighted and thermometer-coded DAC’s. Section Vdeals with the optimization of the architecture for minimumarea. Section VI shows circuit implementation and layoutissues. Section VII presents results from measurements, andSection VIII summarizes the conclusions.II. BINARY WEIGHTED DACFig. 3(a) shows a conceptual circuit of a 10-bit binary-weighted DAC. The digital inputs directly control the switches.The current sources associated with the switches are binaryweighted. The advantage of such a binary-weighted DAC is itssimplicity, as no decoding logic is required. There are severalmajor drawbacks, however, which are all associated withmajor bit transitions. At the mid-code transition (0 111111 1111000 000 000), the most significant bit (MSB) currentsource needs to be matched to the sum of all the othercurrent sources to within 0.5 LSB’s (least significant bits).This is difficult to achieve. Because of statistical spread, suchmatching can never be guaranteed. Therefore this architectureis not guaranteed monotonic. Matching is an issue for all bittransitions, but the severity of the problem is proportionalto the weight of the bit, resulting in a typical differentialnonlinearity (DNL) plot as shown in Fig. 3(b). In addition, theerrors caused by the dynamic behavior of the switches (suchas charge-injection and clock-feedthrough) result in glitchesin the output signal as shown in Fig. 3(c). This problem ismost severe at the midcode transition, as all switches areswitching simultaneously. Such a midcode glitch contains0018–9200/98$10.00 1998 IEEELIN AND BULT: 10-b, 500-MSAMPLE/S CMOS DAC 1949(a)(b)Fig. 1. DAC’s for cable modem applications.Fig. 2. 16-QAM spectrum including an aliased harmonics 47 dB below thefundamental.highly nonlinear signal components, even for small outputsignals and will manifest itself as spurs in the frequencydomain.III. THERMOMETER CODED DACFig. 4(a) shows an example of a 10-bit thermometer-codedDAC. There areunit current sources. Each unitcurrent source is connected to a switch controlled by the signalcoming from the binary-to-thermometer decoder. When thedigital input increases by 1 LSB, one more current sourceis switched from the negative to the positive side. Assumingpositive-only current sources, the analog output is alwaysincreasing as the digital input increases. Hence, monotonicityis guaranteed using this architecture.In addition, there are several other
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