1948 IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 33 NO 12 DECEMBER 1998 A 10 b 500 MSample s CMOS DAC in 0 6 mm Chi Hung Lin and Klaas Bult Abstract A 10 b current steering CMOS digital to analog converter DAC is described with optimized performance for frequency domain applications For sampling frequencies up to 200 MSample s the spurious free dynamic range SFDR is better than 60 dB for signals from dc to Nyquist For sampling frequencies up to 400 MSample s the SFDR is better than 55 dB for signals from dc to Nyquist The measured differential nonlinearity and integral nonlinearity are 0 1 least significant bit LSB and 0 2 LSB respectively The circuit is fabricated in a 0 35 m single poly four metal 3 3V standard digital CMOS process and occupies 0 6 mm2 When operating at 500 MSample s it dissipates 125 mW from a 3 3 V power supply This DAC is optimized for embedded applications with large amounts of digital circuitry Index Terms CMOS analog integrated circuits digital analog conversion matching mixed analog digital integrated circuits I INTRODUCTION T HE pressure to reduce cost in mass market communication devices such as cable modems and digital cable set top boxes has created a need for embedded high speed high resolution digital to analog converters DAC s With the ability to integrate analog circuits with memory and digital signal processing DSP circuits on the same die CMOS technology is poised to meet that challenge In the past 20 years much research has been devoted to DAC s 1 8 optimized for time domain applications such as high resolution displays for computer graphics and high definition television HDTV These DAC s were mainly focused on dc linearity settling behavior and glitch energy performance When used to synthesize sinewaves in frequency domain applications however their spurious free dynamic range SFDR performance is typically not sufficient for broad band applications As an example a simplified architecture of a cable modem headend transmitter is shown in Fig 1 The cable modem system consists of multiple channels where each channel contains a digital modulator and a DAC The channels can have different digital modulation schemes for example quadrature amplitude modulation QAM or quadrature phase shift keying QPSK Without a high speed high resolution DAC these modulation functions must be implemented in the analog domain which generally results in relatively poor quality signals When multiple channels are combined simultaneously it is very important that the DAC s meet a minimum SFDR or signals in one channel will be corrupted by spurious comManuscript received June 25 1998 revised August 19 1998 The authors are with the Broadcom Corporation Irvine CA 92618 USA e mail chlin broadcom com bult broadcom com Publisher Item Identifier S 0018 9200 98 08566 7 ponents from other channels Therefore the major challenge for designing DAC s for frequency domain applications is to obtain large wideband SFDR Fig 2 shows an example of a 16 QAM spectrum for cable modem upstream signals The transmitted signal frequencies range from 5 65 MHz The specification of the multimedia cable network system MCNS requires the aliased harmonics to be at least 47 dB below the fundamental signal Experimental results have shown that this number translates into an SFDR of more than 52 dB for a single tone sinewave That is a difficult requirement to meet for DAC s operating at high signal frequencies The goal of the DAC reported here is to obtain true 10 bit performance SFDR 60 dB for signals from dc to Nyquist for sampling speeds up to 200 MSample s For embedded applications use of standard digital CMOS processes and a small chip area is a must The chip area of this DAC is 0 6 mm in a 0 35 m single poly four metal 3 3 V standard digital CMOS process Sections II and III discuss the advantages and shortcomings of binary weighted DAC s and thermometer coded DAC s respectively Section IV compares the area requirement for these binary weighted and thermometer coded DAC s Section V deals with the optimization of the architecture for minimum area Section VI shows circuit implementation and layout issues Section VII presents results from measurements and Section VIII summarizes the conclusions II BINARY WEIGHTED DAC Fig 3 a shows a conceptual circuit of a 10 bit binaryweighted DAC The digital inputs directly control the switches The current sources associated with the switches are binary weighted The advantage of such a binary weighted DAC is its simplicity as no decoding logic is required There are several major drawbacks however which are all associated with major bit transitions At the mid code transition 0 111 111 111 1 000 000 000 the most significant bit MSB current source needs to be matched to the sum of all the other current sources to within 0 5 LSB s least significant bits This is difficult to achieve Because of statistical spread such matching can never be guaranteed Therefore this architecture is not guaranteed monotonic Matching is an issue for all bit transitions but the severity of the problem is proportional to the weight of the bit resulting in a typical differential nonlinearity DNL plot as shown in Fig 3 b In addition the errors caused by the dynamic behavior of the switches such as charge injection and clock feedthrough result in glitches in the output signal as shown in Fig 3 c This problem is most severe at the midcode transition as all switches are switching simultaneously Such a midcode glitch contains 0018 9200 98 10 00 1998 IEEE LIN AND BULT 10 b 500 MSAMPLE S CMOS DAC 1949 a b Fig 1 DAC s for cable modem applications Fig 2 16 QAM spectrum including an aliased harmonics 47 dB below the fundamental a highly nonlinear signal components even for small output signals and will manifest itself as spurs in the frequency domain b III THERMOMETER CODED DAC Fig 4 a shows an example of a 10 bit thermometer coded unit current sources Each unit DAC There are current source is connected to a switch controlled by the signal coming from the binary to thermometer decoder When the digital input increases by 1 LSB one more current source is switched from the negative to the positive side Assuming positive only current sources the analog output is always increasing as the digital input increases Hence monotonicity is guaranteed using this architecture In addition there are several other advantages for a thermometer coded DAC compared to its binary weighted counterpart First the matching requirement
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