EE247 Lecture 16 D A converters continued Current based DACs unit element versus binary weighted Static performance Component matching systematic random errors Practical aspects of current switched DACs Segmented current switched DACs DAC self calibration techniques Current copiers Dynamic element matching ADC Converters Sampling Sampling switch induced distortion Sampling switch charge injection EECS 247 Lecture 16 Data Converters 2005 H K Page 1 Current Source DAC Unit Element Iref Iout Iref Iref Iref Unit elements 2B 1 current sources switches Monotonicity does not depend on element matching Suited for both MOS and BJT technologies Output resistance of current source causes gain error EECS 247 Lecture 16 Data Converters 2005 H K Page 2 Current Source DAC Unit Element R Vout Iref Iref Iref Iref Output resistance of current source gain error problem Use transresistance amplifier Current source output held virtual ground Error due to current source output resistance eliminated New issues offset speed of the amplifier EECS 247 Lecture 16 Data Converters 2005 H K Page 3 Current Source DAC Binary Weighted 2B 1 Iref Iout 4 Iref 2Iref Iref Binary weighted B current sources switches 2B 1 unit current sources but less of switches Monotonicity depends on element matching EECS 247 Lecture 16 Data Converters 2005 H K Page 4 Static DAC INL DNL Errors Component matching Systematic errors Finite current source output resistance Contact resistance Edge effects in capacitor arrays Process gradient Random errors Lithography Often Gaussian distribution central limit theorem Ref C Conroy et al Statistical Design Techniques for D A Converters JSSC Aug 1989 pp 1118 28 EECS 247 Lecture 16 Data Converters 2005 H K Page 5 Probability density p x Gaussian Distribution 0 4 0 35 0 3 0 25 0 2 0 15 0 1 0 05 0 x 2 p x 1 2 e 2 3 2 1 0 1 2 3 x 2 where standard deviation E x2 2 EECS 247 Lecture 16 Data Converters 2005 H K Page 6 P X x X 1 X 2 X e x2 2 dx Probability density p x Yield P X x X X erf 2 0 4 0 3 0 2 0 1 0 1 0 8 0 6 0 4 0 2 0 95 4 68 3 38 3 0 0 5 1 1 5 2 2 5 3 X EECS 247 Lecture 16 Data Converters 2005 H K Page 7 Yield X 0 2000 0 4000 0 6000 0 8000 1 0000 1 2000 1 4000 1 6000 1 8000 2 0000 P X x X 15 8519 31 0843 45 1494 57 6289 68 2689 76 9861 83 8487 89 0401 92 8139 95 4500 EECS 247 Lecture 16 Data Converters X 2 2000 2 4000 2 6000 2 8000 3 0000 3 2000 3 4000 3 6000 3 8000 4 0000 P X x X 97 2193 98 3605 99 0678 99 4890 99 7300 99 8626 99 9326 99 9682 99 9855 99 9937 2005 H K Page 8 Example Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with 2mV and 0 Fraction of opamps with Vos 6mV X 3 99 73 yield Fraction of opamps with Vos 400 V X 0 2 15 85 yield EECS 247 Lecture 16 Data Converters 2005 H K Page 9 Component Mismatch Example Side by side resistors Large of devices measured curved typically if sample size is large shape is Gaussian No of resistors 400 300 R 200 R 100 0 988 992 996 1000 1004 1008 1012 R E g Let us assume in this example large of Rs with average of 1000OHM measured 68 5 within 4OHM or 0 4 of average 1 for resistors 0 4 EECS 247 Lecture 16 Data Converters 2005 H K Page 10 Probability density p x Component Mismatch Two side by side Resistors R R1 R2 2 0 4 0 35 0 3 0 25 R 0 2 R 0 15 0 1 0 05 0 3 2 dR R1 R2 d2R R 0 2 For typical technologies geometries 1 for resistors 0 02 5 1 Area 3 dR R In the case of resistors is a function of area EECS 247 Lecture 16 Data Converters 2005 H K Page 11 DNL Unit Element DAC E g Resistor string DAC Vref Rmedian I ref Iref i Ri I r e f DNLi median i median Ri R median R median dR R median dR Ri i Ri I ref DNL d Ri Ri DNL of unit element DAC is independent of resolution EECS 247 Lecture 16 Data Converters 2005 H K Page 12 DNL Unit Element DAC E g Resistor string DAC Example If dR R 0 4 what DNL spec goes into the datasheet so that 99 9 of all converters meet the spec DNL d R i Ri DNL of unit element DAC is independent of resolution Note similar results for all unit element based DACs EECS 247 Lecture 16 Data Converters 2005 H K Page 13 Yield X 0 2000 0 4000 0 6000 0 8000 1 0000 1 2000 1 4000 1 6000 1 8000 2 0000 P X x X 15 8519 31 0843 45 1494 57 6289 68 2689 76 9861 83 8487 89 0401 92 8139 95 4500 EECS 247 Lecture 16 Data Converters X 2 2000 2 4000 2 6000 2 8000 3 0000 3 2000 3 4000 3 6000 3 8000 4 0000 P X x X 97 2193 98 3605 99 0678 99 4890 99 7300 99 8626 99 9326 99 9682 99 9855 99 9937 2005 H K Page 14 DNL Unit Element DAC Example If dR R 0 4 what DNL spec goes into the datasheet so that 99 9 of all converters meet the spec E g Resistor string DAC DNL d R i Ri Answer From table for 99 9 X 3 3 DNL dR R 0 4 3 3 DNL 1 3 DNL 0 013 LSB EECS 247 Lecture 16 Data Converters 2005 H K Page 15 DAC INL Analysis Output LSB N B E n A n N 2B 1 Input LSB A n E Ideal n B N n E N n Variance n 2 N n 2 E A n r n N N A B A r A B A 1 r B r Variance of E E2 1 r 2 2 r 2 B2 N r 1 r 2 EECS 247 Lecture 16 Data Converters 2005 H K Page 16 DAC INL n E 2 n 1 2 N To find m a x v a r i a n c e n N 2 d E 2 dn 0 Error is maximum at mid scale N 2 INL 1 2B 1 2 with N 2 B 1 INL depends on DAC resolution and element matching While DNL Ref Kuboki et al TCAS 6 1982 EECS 247 Lecture 16 Data Converters 2005 H K Page 17 Untrimmed DAC INL Example INL 1 B 2 1 2 B 2 2 log2 INL EECS 247 Lecture 16 Data Converters Assume the following requirement INL 0 1 …
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