EE247 Lecture 26 Administrative EE247 Final exam Date Time Location Extra office hours Mon Dec 18th 12 30pm 3 30pm 241 Cory Hall Thurs Dec 14th 10 30am 12pm Closed book course notes No calculators cell phones PDAs computers Bring two 8x11 paper with your own notes Final exam covers the entire course material unless specified otherwise EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 1 EE247 Lecture 26 Oversampled ADCs continued 2nd order modulator Dynamic range Practical implementation Effect of various building block nonidealities on the performance Higher order modulators Cascaded modulators multi stage Single loop single quantizer modulators with multi order filtering in the forward path EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 2 Summary of Last Lecture Oversampled ADCs Allows trading speed for resolution No stringent requirements imposed on analog building blocks Takes advantage of low cost low power digital filtering Relaxed transition band requirements for analog anti aliasing filters Further reduction of baseband quantization noise power by combining oversampling with clever use of feedback By simply increasing oversampling ratio 2X increase in sampling ratio 0 5 bit increase in resolution Embedding the quantizer in a 1st order feedback loop 1 5 bit increase is resolution per 2x increase in sampling rate Problem Limit cycle oscillations at levels exceeding quantization noise 2006 H K Page 3 EECS 247 Lecture 26 Oversampling Data Converters Noise Shaping Function 1st Order Limit Cycle Oscillation Ideal Low pass Digital In band spurious tone Filter with f DC input level First Order Noise Shaping fB fN Frequency fs 2 Problem quantization noise becomes periodic in response to low level DC inputs could fall within passband of interest Solution Use dithering inject noise like signal at the input randomizes quantization noise Circuit thermal noise if large enough acts as dither Second order loop EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 4 1st Order Modulator Linearized Model Analysis Y z z 1 X z 1 z 1 E z LPF HPF EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 5 2nd Order Modulator Two integrators in series Single quantizer typically 1 bit Feedback from output to both integrators Tones less prominent compared to 1st order EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 6 2nd Order Modulator Linearized Model Analysis Recursive drivation Yn X n 1 En 2 En 1 En 2 Using the delay operator z 1 Y z z 1 X z 1 z 1 LPF 2 E z HPF EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 7 2nd Order Modulator In Band Quantization Noise NTF z 1 z 1 2 NTF f 2 24 sin f f s B SY 4 for M 1 SQ f NTF z z e 2 2 jfT df B fs 2M fs 2M 1 2 2sin fT 4 df f s 12 1 2 5 M 5 12 4 EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 8 Quantization Noise 2nd Order Modulator vs 1st Order Modulator 2 1 2 3 3 M 12 SY Noise Shaping Function SY Ideal Low pass Digital Filter 2nd Order Noise Shaping 1st Order Noise Shaping 4 1 2 fB Frequency fs 2 5 5 M 12 2006 H K Page 9 EECS 247 Lecture 26 Oversampling Data Converters 2nd Order Modulator Dynamic Range S peak signal power DR 10log 10log X peak noise power SY 1 SX 2 2 SY 2 sinusoidal input STF 1 4 1 2 5 5 M 12 SX 15 M5 SY 2 4 M 16 32 1024 DR 2nd 49 dB 64 dB 139 dB DR 1st 33dB 42dB 87dB 15 15 DR 10log 4 M 5 10log 4 50log M 2 2 DR 11 1dB 50log M 2X increase in M 15dB 2 5 bit increase in DR EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 10 2nd Order Modulator Example Digital audio application Signal bandwidth 20kHz Resolution 16 bit 16 bit 98dB Dynamic Range DR 11 1dB 50log M M min 153 M 256 28 to allow some margin so that thermal noise dominants provides dithering also for ease of digital filter implementation Sampling rate 2x20kHz 5kHz M 12MHz quite reasonable 2006 H K Page 11 EECS 247 Lecture 26 Oversampling Data Converters Limit Cycle Tones in 1st Order 2nd Order Modulator Higher oversampling ratio lower tones 6dB 1st Order Modulator 2nd order much lower tones compared to 1st 2X increase in M decreases the tones by 6dB for 1st order loop and 12dB for 2nd order loop 12dB 2nd Order Modulator Quantization noise Ref B P Brandt et al Second order sigma delta modulation for digital audio signal acquisition IEEE Journal of Solid State Circuits vol 26 pp 618 627 April 1991 R Gray Spectral analysis of quantization noise in a single loop sigma delta modulator with dc input IEEE Trans Commun vol 37 pp 588 599 June 1989 EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 12 Implementation Practical Design Considerations Internal node scaling clipping Effect of finite opamp gain linearity KT C noise Opamp noise Effect of comparator nonidealities Power dissipation considerations EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 13 Switched Capacitor Implementation 2nd Order Nodes Scaled for Maximum Dynamic Range Modification gain of in front of integrators reduce optimize required signal range at the integrator outputs 1 7x input full scale Note Non idealities associated with 2nd integrator and quantizer when referred to the input is attenuated by 1st integrator high gain The only building block requiring low noise and accuracy is the 1st integrator Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 14 2nd Order Modulator Example Switched Capacitor Implementation Dout IN Fully differential front end Two bottom plate integrators 1 bit DAC is made of switches and Vrefs EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 15 Switched Capacitor Implementation 2nd Order Phase 1 Sample inputs on 1st stage C1 sample output of 1st stage on C1 of 2nd stage Comparator compares output of 2nd integrator result of comparison saved on output latch At the end of phase1 S3 opens prior to S1 opening charge injection just DC offset EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 16 Switched Capacitor Implementation 2nd Order Phase 2 Enable feedback from output to input of both integrators Integrate Reset comparator At the end of phase 2 S4 opens before S2 EECS 247 Lecture 26 Oversampling Data Converters 2006 H K Page 17 2nd Order Modulator Switched Capacitor Implementation The loss in front of each integrator implemented by choice of C2 2C1 f0intg fs 4 EECS 247 Lecture 26
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