EE247 Lecture 11 Switched Capacitor Filters continued Effect of non idealities Bilinear switched capacitor filters Filter design summary Comparison of various filter topologies Data Converters EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 1 Summary Last Lecture Switched capacitor filter design considerations DDI LDI Integrator characteristics Bottom plate LDI integrator overcomes parasitic sensitivity issues Continuous time and complex conjugate terminations Use of T networks to implement high capacitor ratios Switched capacitor filters utilizing double sampling technique Effect of non idealities Opamp finite gain Opamp finite bandwidth Finite slew rate of the opamp this lecture EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 2 Switched Capacitor Direct Transform Discrete DDI Integrator Vin 1 CI 2 Cs 1 1 2 Vo T 1 fs Vo Cs z 1 z C I 1 z 1 Vin Cs 1 C I z 1 EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 3 DDI Switched Capacitor Integrator Vin 1 CI 2 Cs Vo z Cs z 1 CI 1 z 1 Vi n Cs C I 1 Vo z e j T 1 1 e j T j T 2 Cs j eT 2 j T 2 CI e e sin ce si n e j e j 2j Cs 1 jC e j T 2 2 s i n T 2 I Cs 1 C I j T Ideal Integrator T 2 sin T 2 e j T 2 Magnitude Error EECS 247 Lecture 11 S C Filters Data Converters e Phas Error 2006 H K Page 4 DDI Switched Capacitor Integrator Vin 1 CI 2 1 Cs Vo Example Mag phase error for 1 f max sig fs 1 12 Mag error 1 or 0 1dB Phase error T 2 f fs 12 radian 15 degree Qintg 1 phase error in radian Lecture 5 page 1 Qintg 12 3 8 2 f fs 1 32 Mag error 0 16 or 0 014dB Phase error T 2 f fs 32 radian 5 6 degree Qintg 32 10 2 DDI Integrator Magnitude error no problem Phase error major problem EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 5 LDI Switched Capacitor Integrator LDI Lossless Discrete Integrator same as DDI but output is sampled Vin clock cycle earlier LDI V o2 z Cs z 1 2 CI 1 z 1 Vi n z e 1 j T CI 2 Cs 2 Vo2 j T 2 Cs Cs C e j T C j T 2 1 j T 2 I I 1 e e e Cs 1 jC I 2 si n T 2 Cs 1 C I j T Ideal Integrator T 2 si n T 2 No Phase Error For signals at frequencies sampling freq Magnitude error negligible Magnitude Error EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 6 Switched Capacitor Integrator Parasitic Sensitivity Vin 1 CI 2 Cp3 Vo Cp2 Cs Cp1 Effect of parasitic capacitors 1 Cp1 driven by opamp o k 2 Cp2 at opamp virtual gnd o k 3 Cp3 Charges to Vin discharges into CI Problem parasitic sensitivity EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 7 Parasitic Insensitive Bottom Plate Switched Capacitor Integrator Sensitive parasitic cap Cp1 rearrange circuit so that Cp1 does not charge discharge 1 1 Cp1 grounded 2 1 Cp1 at virtual ground Cp2 driven by a low impedance source 1 CI 2 Cp1 Vi Cs Vo Cp2 Vi Solution Bottom plate capacitor integrator EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 8 Bottom Plate Switched Capacitor Integrator 1 1 CI 2 Vo1 2 Cs Vo Vi Vo2 Output Input z Transform Vi Vo1 on 1 Note Different delay from Vi Vi to either output Special attention needed for input output connections Vi on 1 Vion 2 Cs z 1 CI 1 z 1 1 2 C s z CI 1 z 1 EECS 247 Lecture 11 S C Filters Data Converters Vo2 on 2 1 Cs z 2 CI 1 z 1 C s 1 CI 1 z 1 2006 H K Page 9 Bottom Plate Switched Capacitor Integrator z Transform Model 1 z 1 1 z C1s Vi CI 2 z 1 z 1 1 z 2 1 Input Output z transform 1 1 Vi 1 z Vi Cs CI Vi Cs CI 1 12 Vo1 2 Vo Vo2 1 z z 12 1 z 2 1 z 1 Vo1 z 12 Vo2 LDI EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 10 LDI Switched Capacitor Ladder Filter z s 3 s 4 1 2 1 s 5 1 2 Cs CI C s CI 1 2 1 1 z 2 1 z 1 1 z 2 z z 2 z 1 z 1 C s CI Cs CI 1 1 z 1 2 1 z 2 1 z 1 1 z 2 Cs CI C s CI Delay around integrator loop is z 1 2 z 1 2 1 LDI function EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 11 Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour Opamp finite gain Opamp finite bandwidth Finite slew rate of the opamp Non linearities associated with opamp output input characteristics EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 12 Effect of Opamp Non Idealities Finite DC Gain 1 CI 2 Cs Cs H s fs C I 1 Vi Cs 1 s fs C I a Vi Vo DC Gain a Input Output z transform o H s s o a1 Q a Finite DC gain same effect in S C filters as for C T filters If DC gain not high enough causes lowing of overall Q droop in passband EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 13 Effect of Opamp Non Idealities Finite Opamp Bandwidth 1 Vo CI 2 settling error Cs Vi Vi Vo Unity gain freq Input Output z transform ft 2 time T 1 fs AssumptionOpamp does not slew will be revisited Opamp has only one pole exponential settling Ref K Martin A Sedra Effect of the OPamp Finite Gain Bandwidth on the Performance of SwitchedCapacitor Filters IEEE Trans Circuits Syst vol CAS 28 no 8 pp 822 829 Aug 1981 EECS 247 Lecture 11 S C Filters Data Converters 2006 H K Page 14 Effect of Opamp Non Idealities Finite Opamp Bandwidth 1 Vo CI 2 settling error Cs Vi Vi Vo Unity gain freq Input Output z transform ft 2 time T 1 fs CI k k Z 1 H a ct ual Z H id ea l Z 1 e e C I Cs CI ft wh ere k CI Cs f s ft Opam p unity ga in fre que nc y f s Clo ck fre que nc y Ref K Martin A Sedra Effect of the OPamp Finite Gain Bandwidth on the Performance of SwitchedCapacitor Filters IEEE Trans Circuits Syst vol CAS 28 no 8 pp …
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