EE247 Lecture 28 Administrative Extra office hours next week 563 Cory Wed Dec 12th 2pm 4pm Thurs Dec 13th 10am 12pm Project submission Deadline extended Thurs Dec 13th or Frid Dec 14th If you have chosen to do the project please make an appointment with the instructor for 15mins per each project report to present the results Thurs Dec 13th after 1pm or Frid Dec 14th after 10am EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 1 EE247 Lecture 28 Higher order modulators Cascaded modulators MASH last lecture Forward path multi order filter continued Bandpass modulators Testing of modulator front end Acknowledgements Examples of systems utilizing analog digital interface circuitry not part of final exam EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 2 Higher Order Modulators 2 Multi Order Filter E z H z X z Y z Y z H z 1 X z E z 1 H z 1 H z NTF Y z E z 1 1 H z Zeros of NTF poles of H z can be strategically positioned to suppress in band noise spectrum Approach Design NTF first and solve for H z EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 3 Example Modulator Specification Example Audio ADC Dynamic range Signal bandwidth Nyquist frequency Modulator order Oversampling ratio Sampling frequency DR B fN L M fs fN fs 18 Bits 20 kHz 44 1 kHz 5 64 2 822 MHz The order L and oversampling ratio M are chosen based on SQNR 120dB EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 4 Noise Transfer Function NTF z NTF dB stop band attenuation Rstop 80dB L 5 L 5 Rstop 80 B 20000 b a cheby2 L Rstop B high 20 normalize 0 b b b 1 NTF filt b a 20 Chebychev 2 filter chosen zeros in stop band 40 60 80 100 EECS 247 Lecture 28 104 Frequency Hz Oversampled ADCs Cont d Final Remarks 106 2007 H K Page 5 Loop Filter Characteristics H z Loopfilter H dB 100 Y z 1 NTF E z 1 H z 1 H z 1 NFT 80 60 40 20 0 20 4 6 10 10 Frequency Hz EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 6 Modulator Topology Simulation Model Filter X b2 b1 I1 I2 I3 I4 K1 z 1 1 1 z K2 z 1 1 1 z K3 z 1 1 1 z K4 z 1 1 1 z I 1 a1 I 2 a2 I5 I 3 K5 z 1 1 1 z I 4 a3 I 5 a5 a4 Q DAC Gain Comparator g EECS 247 Lecture 28 Y 1 1 Oversampled ADCs Cont d Final Remarks 2007 H K Page 7 Loop filter peak voltages V Internal Node Voltages Internal signal peak amplitudes are weak function of input level except near overload 10 5 0 Maximum peak topeak voltage swing approach 10V Exceed supply voltage 5 i1 i2 i3 i4 i5 q 10 15 20 40 35 30 EECS 247 Lecture 28 Integrator outputs Quantizer input 25 20 15 Input dBV 10 5 0 Solutions Reduce Vref Node scaling Oversampled ADCs Cont d Final Remarks 2007 H K Page 8 Node Scaling Example 3rd Integrator Output Voltage Scaled by K3 b1 a3 K4 b2 Vnew Vold b1 b2 K1 z 1 1 1 z I1 X K2 z 1 1 1 z I2 I 1 a1 K4 z 1 1 1 z I4 K3 z 1 1 1 z I3 I 2 I 3 a2 K5 z 1 1 1 z I5 I 4 I 5 a5 a4 a3 Q DAC Gain g EECS 247 Lecture 28 Comparator Y Oversampled ADCs Cont d Final Remarks 2007 H K Page 9 Node Voltage Scaling 1 5 Loop filter peak voltages V 1 0 5 0 0 5 1 1 5 40 35 30 25 20 15 Input dBV 10 5 0 1 10 k1 1 10 k2 1 k3 1 4 k4 1 4 k5 1 8 a1 1 a2 1 2 a3 1 2 a4 1 4 a5 1 4 b1 1 512 b2 1 16 1 64 g 1 Integrator output range reasonable for new parameters But maximum input signal limited to 5dB 7dB with safety fix EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 10 Input Range Scaling Increasing the DAC levels by using higher value for g reduces the analog to digital conversion gain 1 DOUT z H z 1 gH z g VIN z Loop Filter H z VIN Comparator DOUT 1 or 1 g Increasing VIN g by the same factor leaves 1 Bit data unchanged EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 11 Scaled Stage 1 Model Loop filter peak voltages V 1 5 g modified From 1 to 2 5 1 Overload 0 5 input level shifted up by 8dB 0 0 5 1 1 5 40 35 30 25 20 15 Input dBV EECS 247 Lecture 28 10 5 0 2dB Oversampled ADCs Cont d Final Remarks 2007 H K Page 12 Stability Analysis not included in final exam e kT x kT H z q kT Geff y kT Quantizer Model Approach linearize quantizer and use linear system theory One way of performing stability analysis use RLocus in Matlab with H z as argument and Geff as variable Effective quantizer gain 2 G2 y eff q2 Can obtain Geff from simulation Ref R W Adams and R Schreier Stability Theory for Modulators in Delta Sigma Data Converters S Norsworthy et al eds IEEE Press 1997 EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 13 Stability Analysis G H z 1 G H z N z H z D z G N z STF D z G N z STF Zeros of STF same as zeros of H z Poles of STF vary with G For G 0 no feedback poles of the STF same as poles of H z For G large poles of STF move towards zeros of H z Draw root locus for G values for which poles move to LHP s plane or inside unit circle z plane system is stable EECS 247 Lecture 28 Oversampled ADCs Cont d Final Remarks 2007 H K Page 14 Modulator z Plane Root Locus z Plane Root Locus 0 4 Increasing Geff As Geff increases poles of STF move from poles of H z Geff 0 to zeros of H z Geff 0 3 0 2 0 1 Geff 0 45 0 Pole locations inside unit circle correspond to stable STF and NTF 0 1 0 2 Unit Circle 0 3 Need Geff 0 45 for stability 0 4 0 6 0 7 0 8 EECS 247 Lecture 28 0 9 1 1 1 Oversampled ADCs Cont d Final Remarks 2007 H K Page 15 Effective Quantizer Gain Geff Large inputs comparator input grows Output is fixed 1 Geff drops …
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