EE247 Lecture 15 D A Converters D A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance DAC Examples Glitches EECS 247 Lecture 15 Data Converters 2004 H K Page 1 R String DAC Advantages Simple fast for 8 10bits Inherently monotonic Compatible with purely digital technologies Disadvantages 2B resistors 2B switches for B bits High element count larger area for B 10bits High settling time for B 10 max 0 25 x 2B RC C Ref M Pelgrom A 10 b 50 MHz CMOS D A Converter with 75 W Buffer JSSC Dec 1990 pp 1347 EECS 247 Lecture 15 Data Converters 2004 H K Page 2 R String DAC Including Interpolation Resistor string DAC Resistor string interpolator increases resolution w o drastic increase in complexity e g 6bit DAC 3 3 Vout Considerations Interpolation string loading of main R string Large R values less loading but lower speed Can use buffers EECS 247 Lecture 15 Data Converters 2004 H K Page 3 R String DAC Including Interpolation Use buffers Issues offset speed EECS 247 Lecture 15 Data Converters 2004 H K Page 4 Static DAC INL DNL Errors Component matching Systematic errors Contact resistance Edge effects in capacitor arrays Process gradient Finite current source output resistance Random errors Lithography Often Gaussian distribution central limit theorem Ref C Conroy et al Statistical Design Techniques for D A Converters JSSC Aug 1989 pp 1118 28 EECS 247 Lecture 15 Data Converters 2004 H K Page 5 Probability density p x Gaussian Distribution 0 4 0 35 0 3 0 25 0 2 0 15 0 1 0 05 0 x 2 p x 1 2 e 2 3 2 1 0 1 2 3 x 2 where standard d e v i a t i o n E X 2 2 EECS 247 Lecture 15 Data Converters 2004 H K Page 6 P X x X 1 X 2 X e x2 2 dx Probability density p x Yield P X x X X erf 2 0 4 0 3 0 2 0 1 0 1 0 8 0 6 0 4 0 2 0 95 4 68 3 38 3 0 0 5 1 1 5 2 2 5 3 X EECS 247 Lecture 15 Data Converters 2004 H K Page 7 Yield X 0 2000 0 4000 0 6000 0 8000 1 0000 1 2000 1 4000 1 6000 1 8000 2 0000 P X x X 15 8519 31 0843 45 1494 57 6289 68 2689 76 9861 83 8487 89 0401 92 8139 95 4500 EECS 247 Lecture 15 Data Converters X 2 2000 2 4000 2 6000 2 8000 3 0000 3 2000 3 4000 3 6000 3 8000 4 0000 P X x X 97 2193 98 3605 99 0678 99 4890 99 7300 99 8626 99 9326 99 9682 99 9855 99 9937 2004 H K Page 8 Example Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with 2mV and 0 Fraction of opamps with Vos X 6mV X 3 99 73 yield we d still test before shipping Fraction of opamps with Vos X 400 V X 0 2 15 85 yield EECS 247 Lecture 15 Data Converters 2004 H K Page 9 Component Mismatch Example Two side by side Resistors No of resistors 400 300 R 200 R 100 Large of devices measured 0 996 1000 1004 1008 1012 curved typically if 988 992 sample size large shape R is Gaussian E g Let us assume in this example 1000 Rs measured 68 5 within 4OHM or 0 4 of average 1 for resistors 0 4 EECS 247 Lecture 15 Data Converters 2004 H K Page 10 Probability density p x Component Mismatch Two side by side Resistors R R1 R2 2 0 4 0 35 0 3 0 25 R 0 2 R 0 15 0 1 0 05 0 3 2 dR R1 R2 d2R R 0 2 For typical technologies geometries 1 for resistors 0 02 5 1 Area 3 dR R In the case of resistors is a function of area EECS 247 Lecture 15 Data Converters 2004 H K Page 11 DNL Unit Element DAC E g Resistor string DAC Rnom I ref Iref i Ri I ref DNLi nom Ri R nom Rnom d Rn o m Rn o m dRnom Ri i Ri I ref DNL dRi Ri DNL of unit element DAC is independent of resolution EECS 247 Lecture 15 Data Converters 2004 H K Page 12 DNL Unit Element DAC E g Resistor string DAC Example If dR R 0 4 what DNL spec goes into the datasheet so that 99 9 of all converters meet the spec DNL d R i Ri Answer From table for 99 9 X 3 3 DNL dR R 0 4 3 3 DNL 1 3 DNL of unit element DAC is independent of resolution DNL 0 013 LSB EECS 247 Lecture 15 Data Converters 2004 H K Page 13 DAC INL Analysis A Ideal n B N n Output Lsb N B A n N n 2 E A n r n N A r A B A 1 r B r Variance of E E2 1 r 2 2 r 2 B2 E n Variance n 2 N 2B 1 Input Lsb N r 1 r 2 Maximum r 0 5 n N 2 Max INL midscale EECS 247 Lecture 15 Data Converters 2004 H K Page 14 DAC INL n E 2 n 1 2 N To find m a x v a r i a n c e n N 2 d E 2 dn 0 Error is maximum at mid scale N 2 INL 1 2B 1 2 with N 2 B 1 INL depends on DAC resolution and element matching While DNL Ref Kuboki et al TCAS 6 1982 EECS 247 Lecture 15 Data Converters 2004 H K Page 15 Untrimmed DAC INL Example INL 1 B 2 1 2 B 2 2 log2 INL EECS 247 Lecture 15 Data Converters INL 0 1 LSB 1 0 5 0 2 0 1 B 8 6 B 10 6 B 13 3 B 15 3 2004 H K Page 16 Simulation Example DNL and INL of 12 Bit converter from converter decision thresholds DNL in LSB 2 1 0 04 0 03 LSB avg 6 7e 005 std dev 0 01 range 0 069 B 1 12 0 1 500 1000 1500 2000 bin 2500 3000 3500 4000 INL 0 3 LSB midscale INL in LSB 2 1 0 2 0 8 LSB avg 0 22 std dev 0 21 range 0 99 0 1 500 1000 1500 2000 bin 2500 3000 3500 4000 EECS 247 Lecture 15 Data Converters 2004 H K Page 17 Binary Weighted DAC INL same as for unit element DAC DNL depends on transition Iout Example 0 to 1 DNL2 d 2 1 to 2 DNL2 3 d 2 Consider MSB transition 0111 1000 EECS 247 Lecture 15 Data Converters 2B 1 Iref 4 Iref 2Iref …
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