EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 1EE247Lecture 15D/A Converters • D/A architecture examples– Unit element– Binary weighted• Static performance– Component matching– Architectures• Unit element• Binary weighted• Segmented– Dynamic element matching• Dynamic performance– Glitches• DAC ExamplesEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 2R-String DAC• Advantages:– Simple, fast for <8-10bits– Inherently monotonic– Compatible with purely digital technologies• Disadvantages:– 2Bresistors & 2Bswitches for B bits à High element count & larger area for B>10bits– High settling time for B > 10:τmax= 0.25 x 2BRC*Ref: M. Pelgrom, “A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer,” JSSC, Dec. 1990, pp. 1347.CEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 3R-String DACIncluding InterpolationResistor string DACResistor string interpolator increases resolution w/o drastic increase in complexitye.g. 6bit DACà 3+3Considerations:Interpolation string loading of main R stringLarge R values à less loading but lower speedCan use buffersVoutEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 4R-String DACIncluding InterpolationUse buffers à Issues: offset & speedEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 5Static DAC INL / DNL Errors• Component matching• Systematic errors– Contact resistance– Edge effects in capacitor arrays– Process gradient– Finite current source output resistance• Random errors– Lithography– Often Gaussian distribution (central limit theorem)*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC Aug. 1989, pp. 1118-28.EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 6Gaussian Distribution-3 -2 -1 0 1 2 300.050.10.150.20.250.30.350.4x /σProbability density p(x)( )22x2221p(x)e2wherestandarddeviation:E(X)µσπσσµ−−==−EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 7Yield()2xX2XPXxX1edx2Xerf2π+−−−≤≤+===∫00.10.20.30.4Probability density p(x)0 0.5 1 1.5 2 2.5 300.20.40.60.81X38.368.395.4P(-X ≤ x ≤ +X)EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 8YieldX/σ P(-X ≤ x ≤ X) [%]0.2000 15.85190.4000 31.08430.6000 45.14940.8000 57.62891.0000 68.26891.2000 76.98611.4000 83.84871.6000 89.04011.8000 92.81392.0000 95.4500X/σ P(-X ≤ x ≤ X) [%]2.2000 97.21932.4000 98.36052.6000 99.06782.8000 99.48903.0000 99.73003.2000 99.86263.4000 99.93263.6000 99.96823.8000 99.98554.0000 99.9937EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 9Example• Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with σ = 2mV and µ = 0.• Fraction of opamps with |Vos| < X = 6mV:– X/σ = 3 à 99.73 % yield (we’d still test before shipping!)• Fraction of opamps with |Vos| < X = 400µV:– X/σ = 0.2 à 15.85 % yieldEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 10Component MismatchRR∆10000100200300400No. of resistors100410081012996992988R[]ΩExample: Two side-by-sideResistorsE.g. Let us assume in this example 1000 Rs measured & 68.5% within +-4OHM or +-0.4% of averageà 1σ for resistorsà 0.4%Large # of devices measured & curved à typically if sample size large shape is GaussianEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 11Component Mismatch12122dRRRRR2dRRR1Areaσ+==−∝RR∆000.050.10.150.20.250.30.350.4Probability density p(x)σ2σ3σ−σ−2σ−3σdRRTwo side-by-sideResistorsFor typical technologies & geometries1σ for resistorsà 0.02 το 5%In the case of resistors σ is a function of areaEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 12DNL Unit Element DACiirefRI∆=DNL of unit element DAC is independent of resolution!E.g. Resistor string DAC:IrefiinomrefiirefnomiinomnomnomnomnomiDNL dRRRIRIDNLRRdRdRRRRσσ∆=∆=∆−∆=∆−==≈=EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 13DNL Unit Element DACExample:If σdR/R= 0.4%, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec? Answer:From table: for 99.9% à X/σ = 3.3σDNL= σdR/R= 0.4%3.3 σDNL= 1.3%àDNL= +/- 0.013 LSBDNL of unit element DAC is independent of resolution!E.g. Resistor string DAC:iiDNLdRRσσ=EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 14DAC INL AnalysisBAN=2B-1nnNOutput/[Lsb]Input/[Lsb]EIdeal VarianceA n nσε2B N-n (N-n)σε2E = A-n r =n/N= A-r(A+B)= A (1-r) -B.rà Variance of E:σE2=(1-r)2.σΑ2+ r 2.σB2=N.r .(1-r).σε2àMaximum @ r =0.5, n=N/2àMax INL @ midscaleEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 15DAC INL• Error is maximum at mid-scale (N/2):• INL depends on DAC resolution and element matching σε • While σDNL= σεRef: Kuboki et al, TCAS, 6/198222E2EBINLBn1nNdTofindmax.variance:0dnnN/2121 2 with N21εεσσσσσ−=×=→==−=−EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 16Untrimmed DAC INLExample:σINL= 0.1 LSBσε= 1% B = 8.6σε= 0.5% B = 10.6σε= 0.2% B = 13.3σε= 0.1% B = 15.3+≅−≅εεσσσσINLBINLB2log22 1221EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 17Simulation Exampleσε= 1%B = 12σINL= 0.3 LSB(midscale)500 1000 1500 2000 2500 3000 3500 4000-1012binDNL [in LSB]DNL and INL of 12 Bit converter (from converter decision thresholds)-0.04 / +0.03 LSB, avg=6.7e-005, std.dev=0.01, range=0.069500 1000 1500 2000 2500 3000 3500 4000-1012binINL [in LSB]-0.2 / +0.8 LSB, avg=0.22, std.dev=0.21, range=0.99EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 18Binary Weighted DAC• INL same as for unit element DAC• DNL depends on transition– Example:0 to 1 àσDNL2= σ(dΙ/Ι)21 to 2 à σDNL2= 3σ(dΙ/Ι)2• Consider MSB transition: 0111 … à 1000 …4 IrefIrefIout2Iref2B-1Iref……………EECS 247 Lecture 15: Data Converters © 2004 H.K. Page 19MOS Device Matchingd1d2ddd1d2ddWthLdWGSthLdIII2dIIIIIddVdIVVI+=−==+−Id1Id2•Current matching depends on:-Device ratio matching à larger area less mismatch effect-Threshold voltage matchingà Larger gate-overdrive less threshold voltage mismatch effectEECS 247 Lecture 15: Data Converters © 2004 H.K. Page 20Current-Switched DACs in
View Full Document