EECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 1EE247Lecture 22ADC Converters– Comparator design (continued)• Comparator architecture examples– Techniques to reduce flash ADC complexity• Interpolating• Folding• Multi-Step ADCs– Two-Step flash– Pipelined ADCsEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 2Summary Last LectureADC Converters– Comparator design • Single-stage high-gain open-loop amplifier• Cascade of open-loop amplifiers• Problem associated with DC offset– Cascaded output series cancellation– Input series cancellation– Offset cancellation through additional input pair plus offset storage capacitors• Latched comparators• Comparator examplesEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 3Comparator with Auto-ZeroRef: I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.Note: Reference & input both differentialEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 4Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.Voffset()CCRe f Re fOffsetVVVVV+−+−−=−−Flash ADCComparator with Auto-ZeroEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 5Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.VoffsetVo()()[]()()()OffsetoP1P2In In C CCCRe f Re foP1P2In InVVAAVV VVSubstituting for from previous cycle:VVVVVAAVVNote: Offset is cancelled & difference betweeninput & reference established+− +−+−+−+−−−=∗−−−−=∗−⎡⎤−⎣⎦Flash ADCComparator with Auto-ZeroEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 6Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.Flash ADCUsing Comparator with Auto-ZeroEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 7Auto-Zero ImplementationRef:I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC March 2000, pp. 318-25EECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 8Comparator ExampleRef: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995• Variation on Yukawa latch used w/o preamp• Good for low resolution ADCs (in this case 1.5bit/stage for a pipeline)• Note: M1, M2, M11, M12 operate in triode mode• M11 & M12 added to vary comparator threshold• Conductance at node X is sum of GM1& GM11xEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 9Comparator Example (continued)Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995Vo1G1G2()( )()( )()()CoxVV V VGW WI1 th R th11 11LCoxVV V VGW WI2 th R th21 11LWCW11ox 1VV V VGI1 I2 R RWL1μμμ−−=× +⎡⎤−⎣⎦−−=× +⎡⎤+⎣⎦⎡⎤−−−→Δ = ×+−⎢⎥⎣⎦Vo1Vo2 • M1, M2, M11, M12 operate in triode mode with all having equal L• Conductance of input devices:• To 1st order, for W1= W2 & W11=W12Vthlatch= W11/W1 x VRwhere VR= VR+-VR-Æ VRfixed W11, 12 varied from comparator to comparatorÆ Eliminates need for resistive dividerEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 10Comparator Example• Used in a pipelined ADC with digital correctionÆno offset cancellation requiredDifferential reference & input• M7, M8 operate in triode region• Preamp gain ~10• Input buffers suppress kick-back•φ1 high Æ Cscharged to VR & φ2B is also high Æ current diverted to latchÆcomparator output in hold mode• φ2highÆ Csconnected to S/Hout & comparator input (VR-S/Hout), current sent to preamp Æ comparator in amplify modeRef: S. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter”IEEE JSSC ,NO. 6, Dec. 1987EECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 11Bipolar Comparator Example• Used in 8bit 400Ms/s & 6bit 2Gb/s flash ADC • Signal amplification during φ1 high, latch operates when φ1 low• Input buffers suppress kick-back & input current• Separate ground and supply buses for front-end preamp Æ kick-back noise reductionRef: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXX, pp. 98 - 99, February 1987Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXXI, pp. 232 - 233, February 1988PreampLatched ComparatorEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 12Reducing Flash ADC ComplexityE.g. 10-bit “straight” flash– Input range: 0 … 1V– LSB = Δ: ~ 1mV – Comparators: 1023 with offset < 1/2 LSB– Input capacitance: 1023 * 100fF = 102pF– Power: 1023 * 3mW = 3WÆ High power dissipation & large area & high input cap.Techniques to reduce complexity & power dissipation :– Interpolation– Folding– Folding & Interpolation– Two-step, pipeliningEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 13Interpolation• Idea– Reduce number of preamps & instead interpolate between preamp outputs• Reduced number of preamps– Reduced input capacitance– Reduced area, power dissipation• Same number of latches (2B-1)• Important “side-benefit”– Decreased sensitivity to preamp offsetÆ Improved DNLEECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 14Flash ADCPreamp OutputZero crossings (to be detected by latches) at Vin=Vref1= 1 ΔVref2= 2 Δ0 0.511.5 2 2.5 3-0.500.5Vin /ΔPreamp Output [V]A2A1VinA2A1Vref1Vref2Vref1Vref2EECS 247 Lecture 22 Interpolating & Folding & Mult-Step ADCs © 2007 H.K. Page 15Simulink
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