EE247 Lecture 24 Administrative EE247 Final exam Date Wed Dec 15th Time 12 30pm 3 30pm Location 289 Cory Closed book course notes No calculators cell phones PDAs Computers Bring one 8x11 paper with your own notes Final exam covers the entire course material EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 1 EE247 Lecture 24 Oversampled ADCs 2nd order modulator Practical implementation Effect of various nonidealities on the performance Higher order modulators Cascaded modulators multi stage Single loop single quantizer modulators with multi order filtering in the forward path EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 2 Oversampled ADCs Last Lecture Oversampled ADCs 1st order modulator Quantization error SQNR analysis Limit cycle oscillation 2nd order modulator Dynamic range Practical implementation Effect of various nonidealities on the performance EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 3 2nd Order Effect of Integrator Finite DC Gain 1 Cs Vi CI 2 H z ideal a Vo H z Finit DC Gain EECS 247 Lecture 24 Oversampling Data Converters Cs z 1 CI 1 z 1 1 a z Cs 1 a Cs CI CI 1 a 1 1 z Cs 1 a CI 2004 H K Page 4 2nd Order Effect of Integrator Finite DC Gain Max signal level a Integrator magnitude response f0 a Low integrator DC gain degrades noise performance If a M oversampling ratio Insignificant degradation in SNR Normally DC gain designed to be M in order to suppress nonlinearities EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 5 2nd Order Effect of Integrator Finite DC Gain Simulation results H0 a finite DC gain a M no degradation in SNR Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 6 2nd Order Effect of Integrator Overall Integrator Gain Inaccuracy Gain of in front of integrators is a function of C1 C2 of the integrator The effect of C1 C2 inaccuracy inspected by simulation EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 7 2nd Order Effect of Integrator Overall Gain Inaccuracy Simulation show gain can vary by 20 w o loss in performance Confirms insensitivity of to component variations Note that for gain 0 65 system becomes unstable SNR drops rapidly Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 8 2nd Order Effect of Integrator Nonlinearities Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 9 2nd Order Effect of Integrator Nonlinearities Simulation for single ended topology Even order nonlinearities can be significantly attenuated by using differential circuit topologies Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 10 2nd Order Effect of Integrator Nonlinearities Simulation for single ended topology Odd order nonlinearities 3rd in this case Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 11 2nd Order Effect of KT C noise v2n 2 1 Cs Vi CI 2 a kT kT 1 4 Cs fs 2 Cs fs Total in band noise kT v 2 n input 4 B Cs fs 2kT Cs M v2n f 2 KT Cs Vo For the example of digital audio with 16 bit 100dB M 256 Cs 1pF 6 Vrms noise If FS 4Vp p d then noise is 107dB almost no degradation in overall SNR Cs 1pF CI 2pF small cap area compared to Nyquist ADC caps Since thermal noise provides some level of dithering better not choose much larger capacitors EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 12 2nd Order Effect of Finite Opamp Bandwidth 1 Vo CI 2 settling error Cs Vi Vi Vo Unity gain freq Input Output z transform fu 1 2 time T 1 fs AssumptionOpamp does not slew Opamp has only one pole exponential settling EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 13 2nd Order Effect of Finite Opamp Bandwidth does not require high opamp bandwidth fu 2fs adequate EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 14 2nd Order Effect of Slew Limited Settling 1 Clock 2 Vo ideal Vo real Slewing Slewing EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 15 2nd Order Effect of Slew Limited Settling AssumptionOpamp settling slew limited Minimum slew rate of 1 2 x fs required Low slew rate degrade SNR rapidly EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 16 2nd Order Effect of Comparator Non Idealities on SD Performance 1 bit A D Single comparator Speed must be adequate for the operating sampling rate Input referred noise same as offset Input referred offset feedback loop suppresses the effect performance not sensitive to input referred offset Hysteresis Minimum overdrive required to change the output EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 17 2nd Order Comparator Hysteresis Hysteresis Minimum overdrive required to change the output EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 18 2nd Order Comparator Hysteresis Comparator hysteresis 40 does not affect SNR E g 1V comparator hysteresis up to 25mV tolerable EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 19 Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces SPICE type simulators normally used to test for gross circuit errors only SPICE type simulators too slow and not accurate enough for performance verification Typically behavioral modeling is used in MATLAB like environments Circuit non idealities either computed or found by using SPICE at subcircuit level Non idealities introduced in the behavioral model one by one first to fully understand the effect of each individually Next step is to add as many of the non idealities as possible simultaneously to verify whether there are interaction among nonidealities EECS 247 Lecture 24 Oversampling Data Converters 2004 H K Page 20 Modulator Testing Should make provisions for testing the modulator AFE separate from the decimator digital back end Data acquisition board used to collect 1 bit
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