EE247 Lecture 24 Interleaved ADCs Oversampled ADCs Why oversampling Pulse count modulation Sigma delta modulation 1 Bit quantization Quantization error noise spectrum SQNR analysis Limit cycle oscillations EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 1 Summary Last Lecture Pipelined ADCs continued Effect gain stage sub DAC non idealities on overall ADC performance Digital calibration continued Correction for inter stage gain nonlinearity Implementation Practical circuits Combining the digital bits Stage implementation Circuits Noise budgeting EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 2 Time Interleaved Converters VIN Extremely fast Typically limited by speed of T H Accuracy limited by mismatch among individual ADCs timing offset gain EECS 247 Lecture 24 Oversampled ADCs 4fs fs T H ADC fs Ts 4 ADC fs 2Ts 4 ADC Digital Output 4 ADCs operating in parallel at sampling frequency fs Each ADC converts on one of the 4 possible clock phases Overall sampling frequency 4fs Note T H has to operate at 4fs Output Combiner Example fs 3Ts 4 ADC 2008 H K Page 3 Oversampled ADCs EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 4 Analog to Digital Converters Two categories Nyquist rate ADCs fsigmax 0 5xfsampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max 12 14bits Oversampled ADCs fsigmax 0 5xfsampling Maximum possible signal bandwidth lower compared to nyquist Maximum achievable resolution high 18 to 20bits EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 5 The Case for Oversampling Nyquist sampling fs Signal narrow transition B Freq AA Filter fs 2B Sampler Nyquist ADC Oversampling fs fN Signal B Freq DSP wide transition fs M fN AA Filter Sampler Oversampled ADC DSP Nyquist rate fN 2B Oversampling rate M fs fN 1 EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 6 Nyquist v s Oversampled Converters Antialiasing X f Input Signal frequency fB Nyquist Sampling fB fs fS 2fB Anti aliasing Filter 2fs frequency Oversampling fB EECS 247 Lecture 24 fS 2fB Oversampled ADCs fs frequency 2008 H K Page 7 Oversampling Benefits No stringent requirements imposed on analog building blocks Takes advantage of the availability of low cost low power digital filtering Relaxed transition band requirements for analog anti aliasing filters Reduced baseband quantization noise power Allows trading speed for resolution EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 8 ADC Converters Baseband Noise For a quantizer with step size and sampling rate fs Quantization noise power distributed uniformly across Nyquist bandwidth fs 2 Ne f NB fB fs 2 f s 2 fB Power spectral density N e f 2 1 fs 1 2 fs e2 Noise is distributed over the Nyquist band fs 2 to fs 2 EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 9 Oversampled Converters Baseband Noise fB SB f fB N e f d f B f B 2 1 df 1 2 fs Ne f 2 fB 12 f s 2 NB wh e re for f B f s 2 2 fs 2 SB0 12 2f S SB SB0 B B0 f M s f whe re M s ov e rsampling ratio 2 fB EECS 247 Lecture 24 fB Oversampled ADCs fB f s 2 2008 H K Page 10 Oversampled Converters Baseband Noise 2f S SB SB0 B B0 f M s f whe re M s ov e rsampling ratio 2 fB 2X increase in M 3dB reduction in SB bit increase in resolution octave oversampling To increase the improvement in resolution Embed quantizer in a feedback loop Noise shaping sigma delta modulation EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 11 Pulse Count Modulation Vin kT Vin kT Nyquist ADC t T 0 1 2 0 1 2 t T Oversampled ADC M 8 Mean of pulse count signal approximates analog input EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 12 Pulse Count Spectrum Magnitude f Signal low frequencies f B fs Quantization error high frequency B fs 2 Separate with low pass filter EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 13 Oversampled ADC Predictive Coding vIN ADC 1 bit DOUT Digital Filter N bit Predictor Quantize the difference signal rather than the signal itself Smaller input to ADC Buy dynamic range Only works if combined with oversampling 1 Bit digital output Digital filter computes average N bit output EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 14 Oversampled ADC f Mf s1 N Signal wide transition B Freq Analog AA Filter f Mf s N E g Pulse Count Modulator Sampler Modulator Decimator narrow transition Digital AA Filter 1 Bit Digital f f s2 N DSP N Bit Digital Decimator Digital low pass filter Removes quantization error for f B Provides anti alias filtering for DSP Narrow transition band high order 1 Bit input N Bit output essentially computes average EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 15 Modulator AFE Objectives Convert analog input to 1 Bit pulse density stream Move quantization error to high frequencies f B Operates at high frequency fs fN M 8 256 typical 1024 Since modulator operated at high frequencies need to keep circuitry simple Modulator EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 16 Sigma Delta Modulators Analog 1 Bit modulators convert a continuous time analog input vIN into a 1 Bit sequence DOUT fs VIN H z DOUT DAC 1b Quantizer comparator Loop filter EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 17 Sigma Delta Modulators The loop filter H can be either switched capacitor or continuous time Switched capacitor filters are easier to implement frequency characteristics scale with clock rate Continuous time filters provide anti aliasing protection fs VIN H z DOUT DAC EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 18 Oversampling A D Conversion fs Input Signal Bandwidth Oversampling 1 bit Modulator fs B fs 2M AFE fs M Decimation n bit Filter fs M fs sampling rate M oversampling ratio Analog front end oversampled noise shaping modulator Converts original signal to a 1 bit digital output at the high rate of 2BXM Digital back end digital filter decimation Removes out of band quantization noise Provides anti aliasing to allow re sampling lower sampling rate EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 19 1st Order Modulator 1st order modulator simplest loop filter an integrator z 1 H z 1 z 1 VIN DOUT DAC Note Non linear system with memory difficult to analyze EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 20 1st Order Modulator Switched capacitor implementation 1 2 2 1 0 VIN DOUT 2 2 Full scale input range Note that here is different from Nyquist rate ADC 1LSB EECS 247 Lecture 24 Oversampled ADCs 2008 H K Page 21 1st Order Modulator VIN 2 VIN 2 DOUT 2 or 2 DAC Properties of the 1st order modulator Maximum analog input range is equal to
View Full Document
Unlocking...