EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 1EE247Lecture 17DAC Converters (continued)• DAC dynamic non-idealities• DAC design considerations• Self calibration techniques– Current copiers– Dynamic element matching• DAC reconstruction filterADC Converters•Sampling– Sampling switch induced distortion– Sampling switch charge injectionEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 2Summary of Last Lecture D/A converters continued:– Current based DACs-unit element versus binary weighted– R-2R type DACs– Static performance• Component matching-systematic & random errors– Component variations Æ Gaussian pdf – INL for both unit-element and binary-weighted DACs σDNL= σεx2B/2-1– DNL for unit-element σDNL= σε– DNL for binary-weight DAC: σDNL= σεx2B/2– Practical aspects of current-switched DACs– Segmented current-switched DACsEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 3DAC Dynamic Non-Idealities• Finite settling time– Linear settling issues: (e.g. RC time constants)– Slew limited settling• Spurious signal coupling– Coupling of clock/control signals to the output via switches• Timing error related glitches– Control signal timing skewsEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 4Dynamic DAC Error: Timing Glitch• Consider binary weighted DAC transition 011 Æ 100• DAC output depends on timing• Plot shows situation where the control signals for LSB & MSB– LSB/MSBs on time– LSB early, MSB late– LSB late, MSB early1 1.5 2 2.5 30510Ideal1 1.5 2 2.5 30510Early1 1.5 2 2.5 30510TimeLateEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 5Glitch Energy• Glitch energy (worst case) proportional to: dt x 2B-1 • dt Æ error in timing & 2B-1 associated with half of the switches changing state• LSB energy proportional to: T=1/fs• Need dt x 2B-1<< T or dt << 2-B+1T•Examples:<< 488<< 1.5<< 21216101201000dt [ps]Bfs [MHz]EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 6DAC Dynamic Errors• To suppress effect of non-idealities:– Retiming of current source control signals• Each current source has its own clocked latch incorporated in the current cell • Minimization of latch clock skew by careful layout ensuring simultaneous change of bits– To minimize control and clock feed through to the output via G-D of the switches• Use of low-swing digital circuitryEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 7DAC Implementation Examples• Untrimmed segmented– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC December 1986, pp. 983– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” JSSC March 2001, pp. 315• Current copiers:– D. W. J. Groeneveld et al, “A Self-Calibration Technique for Monolithic High-Resolution D/A Converters,” JSSC December 1989, pp. 1517• Dynamic element matching:– R. J. van de Plassche, “Dynamic Element Matching for High-Accuracy Monolithic D/A Converters,” JSSC December 1976, pp. 795EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 82μ tech., 5Vsupply6+2 segmented8x8 arrayEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 9Two sources of systematic error:- Finite current source output resistance- Voltage drop due to finite ground bus resistanceEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 10Current-Switched DACs in CMOS()()()()M1M2 M1 M3 M1M4 M1 M5 M1M2M1M1M1M1M1M1M12GS th1GS GS GS GSGS GS GS GS22GS th21GS th1mGS th2m21 1m2m31 1mVVIkVV4RI,VV7RIVV9RI,VV10RI4RI1VVIk IVV2IgVV4RgII I14Rg127RgII I17Rg12I−==− =−=− =−⎛⎞−−==⎜⎟−⎝⎠=−⎛⎞→= ≈−−⎜⎟⎝⎠⎛⎞→= ≈−−⎜⎟⎝⎠→()()M1M1M1M12m41 1m2m51 1m9RgII19Rg1210RgII I110Rg12⎛⎞=≈−−⎜⎟⎝⎠⎛⎞→= ≈−−⎜⎟⎝⎠Iout•Assumption: RI is small compared to transistor gate overdriveÆ Desirable to have gm small Example: 5 unit element current sourcesVDDI1I2I3I4Rx4IRx3IRx2IM1M2M3M4I5M5RxIEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 11Current-Switched DACs in CMOSExample: INL of 3-Bit unit element DACInput INL [LSB]Example: 7 unit element current source DAC- assume gmR=1/100• If switching of current sources sequential (1-2-3-4-5-6-7)Æ INL= +0.25LSB• If switching of current sources symmetrical (4-3-5-2-6-1-7 )ÆINL = +0.09, -0.058LSB Æ INL reduced by a factor of 2.6-0.100.10.20.31234567Sequential current source switchingSymmetrical current source switching0EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 12Current-Switched DACs in CMOSExample: DNL of 7 unit element DACInput DNL [LSB]Example: 7 unit element current source DAC- assume gamer=1/100• If switching of current sources sequential (1-2-3-4-5-6-7)Æ DNLmax= + 0.15LSB• If switching of current sources symmetrical (4-3-5-2-6-1-7 )Æ DNLmax= + 0.15LSB ÆDNL unchanged-0.2-0.100.10.21234567Sequential current source switchingSymmetrical current source switchingEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 13More recent published DAC using symmetrical switching built in 0.35μ/3V analog/1.9V digital, area x10 smaller compared to previous example(5+5)EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 14• Layout of Current sources -each current source made of 4 devices in parallel each located in one of the 4 quadrants • Thermometer decoder used to convert incoming binary digital control for the 5 MSB bits• Dummy decoder used on the LSB side to match the latency due to the MSB decoderEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 15• Current source layout– MSB current sources layout in the mid sections of the four quad– LSB current sources on the periphery– Two rows of dummy current sources added to create identical environment for devices in the center versus the ones on the outer sectionsEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 16• Note that each current cell has its clocked latch and clock signal laid out to be close to its switch to ensure simultaneous switching of current sources• Special attention paid to the final latch to have the cross point of the complementary switch control signal such that the two switches are not both turned off during transitionEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 17• Measured DNL/INL with current associated with the cells as a variableEECS 247 Lecture 17: Data Converters © 2006 H.K. Page 18EECS 247 Lecture 17: Data Converters ©
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