EE247 Lecture 17 DAC Converters continued DAC dynamic non idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch induced distortion Sampling switch charge injection EECS 247 Lecture 17 Data Converters 2006 H K Page 1 Summary of Last Lecture D A converters continued Current based DACs unit element versus binary weighted R 2R type DACs Static performance Component matching systematic random errors Component variations Gaussian pdf INL for both unit element and binary weighted DACs DNL DNL for unit element DNL DNL for binary weight DAC DNL x2B 2 1 x2B 2 Practical aspects of current switched DACs Segmented current switched DACs EECS 247 Lecture 17 Data Converters 2006 H K Page 2 DAC Dynamic Non Idealities Finite settling time Linear settling issues e g RC time constants Slew limited settling Spurious signal coupling Coupling of clock control signals to the output via switches Timing error related glitches Control signal timing skews EECS 247 Lecture 17 Data Converters 2006 H K Page 3 Dynamic DAC Error Timing Glitch Plot shows situation where the control signals for LSB MSB LSB MSBs on time LSB early MSB late LSB late MSB early EECS 247 Lecture 17 Data Converters Ideal 5 0 10 Early DAC output depends on timing 10 1 1 5 2 2 5 3 1 1 5 2 2 5 3 1 1 5 2 2 5 3 5 0 10 Late Consider binary weighted DAC transition 011 100 5 0 Time 2006 H K Page 4 Glitch Energy Glitch energy worst case proportional to dt x 2B 1 dt error in timing 2B 1 associated with half of the switches changing state LSB energy proportional to T 1 fs Need dt x 2B 1 T or dt 2 B 1 T Examples fs MHz B dt ps 1 20 1000 12 16 10 488 1 5 2 EECS 247 Lecture 17 Data Converters 2006 H K Page 5 DAC Dynamic Errors To suppress effect of non idealities Retiming of current source control signals Each current source has its own clocked latch incorporated in the current cell Minimization of latch clock skew by careful layout ensuring simultaneous change of bits To minimize control and clock feed through to the output via G D of the switches Use of low swing digital circuitry EECS 247 Lecture 17 Data Converters 2006 H K Page 6 DAC Implementation Examples Untrimmed segmented T Miki et al An 80 MHz 8 bit CMOS D A Converter JSSC December 1986 pp 983 A Van den Bosch et al A 1 GSample s Nyquist Current Steering CMOS D A Converter JSSC March 2001 pp 315 Current copiers D W J Groeneveld et al A Self Calibration Technique for Monolithic High Resolution D A Converters JSSC December 1989 pp 1517 Dynamic element matching R J van de Plassche Dynamic Element Matching for HighAccuracy Monolithic D A Converters JSSC December 1976 pp 795 EECS 247 Lecture 17 Data Converters 8x8 array EECS 247 Lecture 17 Data Converters 2006 H K Page 7 2 tech 5Vsupply 6 2 segmented 2006 H K Page 8 Two sources of systematic error Finite current source output resistance Voltage drop due to finite ground bus resistance EECS 247 Lecture 17 Data Converters 2006 H K Page 9 Current Switched DACs in CMOS I1 k VG SM 1 Vth VG SM 2 VG SM 1 4RI VG SM 3 VGSM 1 7R I VG SM 4 VG SM 1 9R I VG SM 5 VG SM 1 10R I 2 4R I 2 I 2 k VG SM 2 Vth I1 1 VG SM 1 Vth 2I1 gmM 1 VG SM 1 Vth 2 Iout VDD M1 I1 M2 I2 M3 I3 M4 I4 M 5 I5 2 4R gmM 1 I 2 I1 1 I1 1 4R gmM 1 2 2 7R gmM 1 I 3 I1 1 I1 1 7R gmM 1 2 2 9R gmM 1 I4 I1 1 I1 1 9R gmM 1 2 2 1 0R gmM 1 I5 I1 1 I1 1 10R gmM 1 2 Rx4I Rx3I Rx2I RxI Example 5 unit element current sources Assumption RI is small compared to transistor gate overdrive Desirable to have gm small EECS 247 Lecture 17 Data Converters 2006 H K Page 10 Current Switched DACs in CMOS Example INL of 3 Bit unit element DAC INL LSB 0 3 Sequential current source switching Symmetrical current source switching 0 2 0 1 0 0 1 0 1 2 3 4 5 Input 6 7 Example 7 unit element current source DAC assume gmR 1 100 If switching of current sources sequential 1 2 3 4 5 6 7 INL 0 25LSB If switching of current sources symmetrical 4 3 5 2 6 1 7 INL 0 09 0 058LSB INL reduced by a factor of 2 6 EECS 247 Lecture 17 Data Converters 2006 H K Page 11 Current Switched DACs in CMOS Example DNL of 7 unit element DAC DNL LSB 0 2 0 1 0 0 1 0 2 Sequential current source switching Symmetrical current source switching 1 2 3 4 5 6 7 Input Example 7 unit element current source DAC assume gamer 1 100 If switching of current sources sequential 1 2 3 4 5 6 7 DNLmax 0 15LSB If switching of current sources symmetrical 4 3 5 2 6 1 7 DNLmax 0 15LSB DNL unchanged EECS 247 Lecture 17 Data Converters 2006 H K Page 12 5 5 More recent published DAC using symmetrical switching built in 0 35 3V analog 1 9V digital area x10 smaller compared to previous example EECS 247 Lecture 17 Data Converters 2006 H K Page 13 Layout of Current sources each current source made of 4 devices in parallel each located in one of the 4 quadrants Thermometer decoder used to convert incoming binary digital control for the 5 MSB bits Dummy decoder used on the LSB side to match the latency due to the MSB decoder EECS 247 Lecture 17 Data Converters 2006 H K Page 14 Current source layout MSB current sources layout in the mid sections of the four quad LSB current sources on the periphery Two rows of dummy current sources added to create identical environment for devices in the center versus the ones on the outer sections EECS 247 Lecture 17 Data Converters 2006 H K Page 15 Note that each current cell has its clocked latch and clock signal laid out to be close to its switch to ensure simultaneous switching of current sources Special attention paid to the final latch to have the cross point of the complementary switch control signal such that the two switches are not both turned off during transition EECS 247 Lecture 17 Data Converters 2006 H K Page 16 Measured DNL INL with current associated with the cells as a variable EECS 247 Lecture 17 Data Converters 2006 H K Page 17 EECS 247 Lecture 17 Data Converters 2006 H K Page 18 16bit DAC 6 10 MSB DAC uses calibrated current sources I 2 Current Divider I 2 I EECS 247 Lecture 17 Data …
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