EECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 1EE247Lecture 13• Data Converters– Static testing (continued)• ………………..• Histogram testing– Dynamic tests• Spectral testingÆ Reveals ADC errors associated with dynamic behavior i.e. ADC performance as a function of frequency– Direct Discrete Fourier Transform (DFT) based measurements utilizing sinusoidal signals– DFT measurements including windowingEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 2Summary Last Lecture• Data converters– Static converter error sources•Offset• Full-scale error• Differential non-linearity (DNL)• Integral non-linearity (INL)– Measuring DNL & INL• Servo-loop• Code density testing (histogram testing)EECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 3Histogram Testing• Histogram testing– Quantize input with known pdf (e.g. ramp or sinusoid)– Measure output pdf– Derive INL and DNL from deviation of measured pdf from expected resultEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 4Histogram Test SetupRamp0VREFADC PCVREF• Slow (wrt conversion time) linear ramp applied to ADC• DNL derived directly from total number of occurrences of each code @ the output of the ADCTimefSEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 5A/D Histogram Test Using Ramp SignalDigital OutputAnalog inputRampTimen/fsADCInput/OutputExample:Ramp slope: 10μV/μsec1LSB =10mVEach ADC code Æ1msecfs =100kHz Æ Ts=10μsecÆ n =100 samples/codeEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 6A/D Histogram Test Using Ramp SignalDigital OutputAnalog inputRampTimen/fsADCInput/OutputExample:Ramp slope: 10μV/usec1LSB =10mVEach ADC codeÆ1msecfs =100kHz Æ Ts=10μsecÆn =100 samples/codeÆMeasurement resolution Æ n# ofSamplesPer codeDigitalOutputEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 7Ramp HistogramExample: Ideal 3-Bit ADC0 1 2 3 4 5 6 7 801234567ADC characteristicsideal converter0 1 2 3 4 5 6 7020406080100120140160180200ADC output codeCode CountDigital Output CodeADC Input Voltage [Δ]EECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 8Ramp HistogramExample: Real 3-Bit ADC Including Non-Idealities0 1 2 3 4 5 6 7 801234567ADC characteristicsideal converter+0.4 LSB DNL-0.4 LSB DNL+0.4 LSB INL0 1 2 3 4 5 6 7020406080100120140160180200ADC output codeCode CountDigital Output CodeADC Input Voltage [Δ]EECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 9Example: 3 Bit ADCDNL Extracted from Histogram1- Remove “Over-range bins”(0 and full-scale) 2- Compute average count/bin (600/6=100 in this case)0 1 2 3 4 5 6 7020406080100120140ADC output codeCode Count, End bins removedEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 10Example: 3 Bit ADCProcess of Extracting from Histogram3- Normalize:- Divide histogram by average count/binÆ ideal bins have exactly the average count, which, after normalization, would be 1Æ Non-ideal bins would have a normalized value greater of smaller than 1 0 1 2 3 4 5 6 700.20.40.60.811.21.4ADC output codeNormalized Code CountEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 11Example: 3 Bit ADCDNL Extracted from Histogram4- Subtract 1 from the normalized code count5- Result Æ DNL (+-0.4Lsb in this case)0 1 2 3 4 5 6 7-0.4-0.3-0.2-0.100.10.20.30.4ADC output codeDNL = Counts / Mean(Counts) -1 EECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 12Example: 3-Bit ADCStatic Characteristics Extracted from Histogram• DNL histogram Æused to reconstruct the exact converter characteristic (having measured only the histogram)• Width of all codesderived from measured DNL (Code=DNL + 1LSB)0 1 2 3 4 5 6 701234567ADC Input VoltageDigital OutputReconstructed ADC Transfer CharacteristicEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 13Example: 3 Bit ADCDNL & INL Extracted from Histogram0 1 2 3 4 5 6 701234567ADC characteristicsIdeal converter+0.4 LSB DNL-0.4 LSB DNL+0.4 LSB INL1 2 3 4 5 6-1-0.500.51DNL [LSB]1 2 3 4 5 6Digital Output CodeINL [LSB]Digital Output CodeADC Input Voltage [Δ]-1-0.500.51EECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 14ADC Histogram Testing Sinusoidal Inputs• Ramp signal generators linear to only 8 to10bitsÆ Need to find input signal with better purity• Solution: ÆUse sinusoidal test signal (may need to filter out harmonics)• Problem: Ideal ADC histogram not flat but has “bath-tub shape”1000 2000 3000 400005001000ADC Output- Raw Histogram ADC output codeCode CountEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 15ADC Histogram Test Using Sinusoidal SignalsSinusoidAt sinusoid midpoint crossings:dv/dt Æ max.Æ least # of samplesAt sinusoid amplitude peaks:dv/dt Æ min.Æ highest # of samplesADCInput/OutputDigital OutputAnalog inputTime# ofSamplesPer codeDigitalOutputEECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 16Correction for Sinusoidal PDF• References:– [1] M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic Testing and Diagnostics of A/D Converters,” IEEE Transactions on Circuits and Systems, vol. CAS-33, no. 8, Aug. 1986.– [2] IEEE Standard 1057• Is it necessary to know the exact amplitude and offset of sinusoidal input? No!EECS 247 Lecture 13: Data Converters- Static & Dynamic Testing © 2007 H. K. Page 17DNL/INL Extraction Matlab Programfunction [dnl,inl] = dnl_inl_sin(y);%DNL_INL_SIN% dnl and inl ADC output% input y contains the ADC output% vector obtained from quantizing a% sinusoid% Boris Murmann, Aug 2002% Bernhard Boser, Sept 2002% histogram boundariesminbin=min(y);maxbin=max(y);% histogramh = hist(y, minbin:maxbin);% cumulative histogramch = cumsum(h);% transition levels found by:T = -cos(pi*ch/sum(h));% linearized
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