EE247 Lecture 13 Data Converters Static testing continued Histogram testing Dynamic tests Spectral testing Reveals ADC errors associated with dynamic behavior i e ADC performance as a function of frequency Direct Discrete Fourier Transform DFT based measurements utilizing sinusoidal signals DFT measurements including windowing EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 1 Summary Last Lecture Data converters Static converter error sources Offset Full scale error Differential non linearity DNL Integral non linearity INL Measuring DNL INL Servo loop Code density testing histogram testing EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 2 Histogram Testing Histogram testing Quantize input with known pdf e g ramp or sinusoid Measure output pdf Derive INL and DNL from deviation of measured pdf from expected result EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 3 Histogram Test Setup VREF fS Ramp VREF ADC 0 PC Time Slow wrt conversion time linear ramp applied to ADC DNL derived directly from total number of occurrences of each code the output of the ADC EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 4 A D Histogram Test Using Ramp Signal Digital Output Example ADC Input Output Ramp slope 10 V sec 1LSB 10mV Each ADC code 1msec fs 100kHz Ts 10 sec Analog input n 100 samples code n fs Ramp Time EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 5 Example Ramp slope 10 V usec 1LSB 10mV Each ADC code 1msec Digital Output A D Histogram Test Using Ramp Signal Analog input fs 100kHz Ts 10 sec of Samples Per code Time n fs n 100 samples code Measurement resolution n EECS 247 Lecture 13 ADC Input Output Data Converters Static Dynamic Testing Ramp Digital Output 2007 H K Page 6 Ramp Histogram Example Ideal 3 Bit ADC 7 200 ADC characteristics ideal converter 180 160 Code Count Digital Output Code 6 5 4 3 140 120 100 80 2 60 1 40 0 20 0 1 2 3 4 5 6 ADC Input Voltage EECS 247 Lecture 13 7 0 8 0 1 2 3 4 5 6 7 ADC output code Data Converters Static Dynamic Testing 2007 H K Page 7 Ramp Histogram Example Real 3 Bit ADC Including Non Idealities 7 180 160 6 0 4 LSB DNL 140 5 Code Count Digital Output Code 200 ADC characteristics ideal converter 120 4 100 3 0 4 LSB INL 2 80 60 1 40 0 4 LSB DNL 20 0 0 1 2 3 4 5 6 ADC Input Voltage EECS 247 Lecture 13 7 8 0 0 1 Data Converters Static Dynamic Testing 2 3 4 5 6 7 ADC output code 2007 H K Page 8 Example 3 Bit ADC 1 Remove Over range bins 0 and full scale 2 Compute average count bin 600 6 100 in this case Code Count End bins removed DNL Extracted from Histogram 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 ADC output code EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 9 Example 3 Bit ADC Process of Extracting from Histogram 3 Normalize Divide histogram by average count bin ideal bins have exactly the average count which after normalization would be 1 Non ideal bins would have a normalized value greater of smaller than 1 Normalized Code Count 1 4 1 2 1 0 8 0 6 0 4 0 2 0 0 1 2 3 4 5 6 7 ADC output code EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 10 4 Subtract 1 from the normalized code count 5 Result DNL 0 4Lsb in this case DNL Counts Mean Counts 1 Example 3 Bit ADC DNL Extracted from Histogram 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 0 1 2 3 4 5 6 7 ADC output code EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 11 Example 3 Bit ADC Static Characteristics Extracted from Histogram 7 6 Digital Output DNL histogram used to reconstruct the exact converter characteristic having measured only the histogram Reconstructed ADC Transfer Characteristic 5 4 3 2 1 0 0 1 2 3 4 5 6 7 Width of all codes ADC Input Voltage derived from EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 12 measured DNL Code DNL 1LSB Example 3 Bit ADC DNL INL Extracted from Histogram ADC characteristics Ideal converter DNL LSB 1 0 5 6 0 4 LSB DNL 0 0 5 5 1 4 3 0 4 LSB INL 1 2 3 4 5 6 3 4 5 6 1 INL LSB Digital Output Code 7 0 5 2 1 0 4 LSB DNL 0 0 5 0 0 1 2 3 4 5 6 1 7 ADC Input Voltage EECS 247 Lecture 13 1 2 Digital Output Code Data Converters Static Dynamic Testing 2007 H K Page 13 ADC Histogram Testing Sinusoidal Inputs Solution Use sinusoidal test signal may need to filter out harmonics Problem Ideal ADC histogram not flat but has bath tub shape EECS 247 Lecture 13 ADC Output Raw Histogram Code Count Ramp signal generators linear to only 8 to10bits Need to find input signal with better purity 1000 500 0 1000 2000 3000 4000 ADC output code Data Converters Static Dynamic Testing 2007 H K Page 14 At sinusoid midpoint crossings dv dt max least of samples Digital Output ADC Histogram Test Using Sinusoidal Signals Analog input of Samples Per code Time At sinusoid amplitude peaks dv dt min highest of samples EECS 247 Lecture 13 ADC Input Output Data Converters Static Dynamic Testing Sinusoid Digital Output 2007 H K Page 15 Correction for Sinusoidal PDF References 1 M V Bossche J Schoukens and J Renneboog Dynamic Testing and Diagnostics of A D Converters IEEE Transactions on Circuits and Systems vol CAS 33 no 8 Aug 1986 2 IEEE Standard 1057 Is it necessary to know the exact amplitude and offset of sinusoidal input No EECS 247 Lecture 13 Data Converters Static Dynamic Testing 2007 H K Page 16 DNL INL Extraction Matlab Program function dnl inl dnl inl sin y DNL INL SIN dnl and inl ADC output input y contains the ADC output vector obtained from quantizing a sinusoid T cos pi ch sum h linearized histogram hlin T 2 end T 1 end 1 truncate at least first and last bin more if input did not clip ADC trunc 2 hlin trunc hlin 1 trunc end trunc Boris Murmann Aug 2002 Bernhard Boser Sept 2002 histogram boundaries minbin min y maxbin max y calculate lsb size and dnl lsb sum hlin trunc length hlin trunc dnl 0 hlin trunc lsb 1 misscodes length find dnl 0 9 histogram h hist y minbin maxbin cumulative histogram ch cumsum h EECS 247 Lecture 13 transition levels found by calculate inl inl cumsum dnl Data Converters Static Dynamic Testing 2007 H K Page 17 Example …
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