EE247 Lecture 17 Nyquist rate ADC converters Sampling Sampling switch considerations Thermal noise due to switch resistance last lecture Clock jitter related non idealities Sampling switch bandwidth limitations Switch induced distortion Sampling switch conductance dependence on input voltage Clock voltage boosters Sampling switch charge injection clock feedthrough EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 1 Practical Sampling Issues 1 vIN vOUT M1 C Switch induced noise due to M1 finite channel resistance Clock jitter Finite Rsw limited bandwidth finite acquisition time Rsw f Vin distortion Switch charge injection clock feedthrough EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 2 Clock Jitter The error voltage is x t actual sampling time tJ e x t0 tJ t0 x t0 error nominal sampling time t0 EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 3 Effect of Clock Jitter on Sampling of a Sinusoidal Signal Sinusoidal input Ampl i t ude Fr equency Ji t t er Worst case A fx dt x t A s i n 2 f xt x t 2 f x Acos 2 f xt A AF S e t dt x t ma x 2 f x A Requi r ement e t x t ma x dt e t 2 f x Adt EECS 247 Lecture 17 f x fs 2 2 2 AF S 2B 1 1 B 2 fs of Bits fs dt 12 16 10 1 MHz 20 MHz 1000 MHz 78 ps 0 24 ps 0 3 ps Nyquist Rate ADCs Sampling 2008 H K Page 4 Law of Jitter The worst case looks pretty stringent what about the average Let s calculate the mean squared jitter error variance If we re sampling a sinusoidal signal x t Asin 2 fxt then x t 2 fxAcos 2 fxt E x t 2 2 2fx2A2 Assume the jitter has variance E tJ t0 2 2 EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 5 Law of Jitter If x t and the jitter are independent E x t tJ t0 2 E x t 2 E tJ t0 2 Hence the jitter error power is E e2 2 2fx2A2 2 If the jitter is uncorrelated from sample to sample this jitter noise is white EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 6 Law of Jitter DR jitter A2 2 2 f x2 A2 2 2 1 2 2 f x2 2 20 log10 2 f x EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 7 Example ADC Spectral Tests SFDR SDR SNR Ref W Yang et al A 3 V 340 mW 14 b 75 Msample s CMOS ADC with 85 dB SFDR at Nyquist input IEEE J of Solid State Circuits Dec 2001 EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 8 More on Jitter In cases where clock signal is provided from off chip have to choose a source with low enough jitter On chip precautions to keep the clock jitter less than single digit pico second Separate supplies as much as possible Separate analog and digital clocks Short inverter chains between clock source and destination Few if any other analog to digital conversion non idealities have the same symptoms as sampling jitter RMS noise proportional to input signal frequency RMS noise proportional to input signal amplitude In cases where clock jitter limits the dynamic range it s easy to tell but may be difficult to fix EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 9 Sampling Acquisition Bandwidth 1 The resistance R of switch S1 turns the sampling network into a lowpass filter with finite time constant vIN R C RC Assuming Vin is constant during the sampling period and C is initially discharged Need to allow enough time for the output to settle to less than 1 ADC LSB determines minimum duration for 1 or maximum clock frequency EECS 247 Lecture 17 vOUT S1 vout t vin 1 e t 1 vin vout Nyquist Rate ADCs Sampling v 2008 H K Page 10 Sampling Effect of Switch On Resistance 1 Vin Vout since Vout Vin 1 e t tx tx Vin e Ts 2 or Ts 1 2 ln Vin vIN R vOUT S1 C Worst Case Vin VFS 1 0 72 Ts Ts 2 ln 2 B 1 B 1 1 1 0 72 R 2 f sC ln 2 B 1 B f s C tx T 1 fS Example B 14 C 13pF fs 100MHz Ts 19 4 or 10 Ts 2 R 40 EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 11 Switch On Resistance Switch MOS operating in triode mode I D triode Cox RON Cox W VDS VGS VTH 2 L dI D triode 1 RON dVDS 1 1 W W VGS Vth Cox VDD Vth Vin L L Let us call R Vin 0 Ro then RON VDS Ro 1 W Cox VDD Vth L Ro Vin 1 VDD Vth EECS 247 Lecture 17 Nyquist Rate ADCs Sampling VDS 0 VGS VDD Vin 1 VDD Vin M1 C 2008 H K Page 12 Sampling Distortion Simulated 10 Bit ADC Ts 2 5 VDD Vth 2V VFS 1V Sampling switch modeled vout T Vin 1 2 VDD Vth vin 1 e Results in HD2 41dBFS HD3 51 4dBFS EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 13 Sampling Distortion Doubling sampling time or time constant Results in HD2 improved from 41dBFS to 70dBFS 30dB HD3 improved from 51 4dBFS to 76 3dBFS 25dB Allowing enough time for the sampling network settling Reduces distortion due to switch R non linear behavior to a tolerable level EECS 247 Lecture 17 10bit ADC Ts 2 10 VDD Vth 2V Nyquist Rate ADCs Sampling VFS 1V 2008 H K Page 14 Sampling Distortion Effect of Supply Voltage 10bit ADC Ts 2 5 VDD Vth 2V VFS 1V 10bit ADC Ts 2 5 VDD Vth 4V VFS 1V Effect of higher supply voltage on sampling distortion HD3 decrease by VDD1 VDD2 2 HD2 decrease by VDD1 VDD2 EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 15 Sampling Distortion SFDR sensitive to sampling distortion improve linearity by Larger VDD VFS Decreased dynamic range if VDD const Larger switches Issue Increased switch charge injection Increased nonlinear S D junction cap Complementary switch Constant max VGS f Vin EECS 247 Lecture 17 10bit ADC Ts 20 VFS 1V VDD Vth 2V Nyquist Rate ADCs Sampling 2008 H K Page 16 Practical Sampling Summary So Far kT C noise C 12k BT 1 22 B VFS 2 vOUT vIN M1 Finite Rsw limited bandwidth 0 72 R B f sC C gsw f Vin distortion Vin gON go 1 VDD Vth EECS 247 Lecture 17 for go Cox W VDD Vth L Nyquist Rate ADCs Sampling 2008 H K Page 17 Sampling Use of Complementary Switches 1 go 1B gon goT gon gop gop 1 1B Complementary n p switch advantages 9Increase in the overall conductance …
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