EECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 1EE247Lecture 17• Nyquist rate ADC converters–Sampling• Sampling switch considerations–Thermal noise due to switch resistance (last lecture)–Clock jitter related non-idealities–Sampling switch bandwidth limitations–Switch induced distortion• Sampling switch conductance dependence on input voltage• Clock voltage boosters–Sampling switch charge injection & clock feedthroughEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 2Practical SamplingIssuesvINvOUTCM1φ1• Switch induced noise due to M1 finite channel resistance• Clock jitter• Finite RswÆ limited bandwidth Æ finite acquisition time• Rsw= f(Vin) Æ distortion• Switch charge injection & clock feedthroughEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 3Clock Jitter• The error voltage isnominalsamplingtime t0actualsamplingtime tJx(t)x’(t0)e = x’(t0)(tJ –t0)errorEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 4Effect of Clock Jitter on Sampling of a Sinusoidal SignalSinusoidal inputWorst case78 ps0.24 ps0.3 ps1 MHz20 MHz1000 MHz121610dt <<fs# of BitssFSxFSB1BsfAAf22Ae( t )221dt2fπ+==Δ<< ≅<<()()xxxxxmaxmaxxAmplitude: AFrequency: f Jitter: dtx( t ) A s i n 2 f tx'(t) 2 f Acos 2 f tx'(t ) 2 f ARequirement:e( t ) x' ( t ) d te( t ) 2 f A d tπππππ==≤≤≤EECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 5Law of Jitter• The worst case looks pretty stringent …what about the “average”?• Let’s calculate the mean squared jitter error (variance)• If we’re sampling a sinusoidal signal x(t) = Asin(2πfxt), then– x’(t) = 2πfxAcos(2πfxt)–E{[x’(t)]2} = 2π2fx2A2• Assume the jitter has variance E{(tJ-t0)2} = τ2EECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 6Law of Jitter• If x’(t) and the jitter are independent– E{[x’(t)(tJ-t0)]2}= E{[x’(t)]2} E{(tJ-t0)2}• Hence, the jitter error power is• If the jitter is uncorrelated from sample to sample, this “jitter noise” is whiteE{e2} = 2π2fx2A2τ2EECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 7Law of Jitter()τπτπτπxxxffAfADR2log202122/1022222222jitter−===EECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 8Example: ADC Spectral Tests SFDRSDRSNRRef: W. Yang et al., "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE J. of Solid-State Circuits, Dec. 2001EECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 9More on Jitter• In cases where clock signal is provided from off-chipÆ have to choose a source with low enough jitter• On-chip precautions to keep the clock jitter less than single-digit pico-second :– Separate supplies as much as possible– Separate analog and digital clocks– Short inverter chains between clock source and destination• Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter:– RMS noise proportional to input signal frequency– RMS noise proportional to input signal amplitudeÆIn cases where clock jitter limits the dynamic range, it’s easy to tell, but may be difficult to fix...EECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 10Sampling Acquisition Bandwidth• The resistance R of switch S1 turns the sampling network into a lowpass filter with finite time constant:τ = RC • Assuming Vinis constant during the sampling period and C is initially discharged• Need to allow enough time for the output to settle to less than 1 ADC LSB Æ determines minimum duration for φ1or maximum clock frequencyvINvOUTCS1φ1R()τ/1)(tinoutevtv−−=φ1vinvoutδ vEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 11Sampling: Effect of Switch On-ResistanceExample:B = 14, C = 13pF, fs= 100MHzTs /τ>> 19.4, or 10τ <<Ts/2 Æ R << 40 Ωφ1T=1/fStx()()()/2since 112lnWorst Case: 10.722ln 2 11 1 0.722ln 2 1stx txtin out out inTsininin FSssBBssVV VV eTVe orVVVTTBRfC Bf Cττττ−−−<<Δ =−→<<Δ<<⎛⎞⎜⎟Δ⎝⎠=×<< ≈−<< ≈−vINvOUTCS1φ1REECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 12Switch On-Resistance() ()()()()01,2111Let us call @ =0 1DSDtriodeDSDtriode ox GS TH DSON DSVONox GS th ox DD th inin o oox DD thoONinDD thdIVWICVVVLRdVRWWCVV CVVVLLRV RthenRWCVVLRRVVVμμμμ→⎛⎞=−− ≅⎜⎟⎝⎠==−−−=−=−−SwitchÆ MOS operating in triode mode:VinCM1φ1ÆVDDVGS =VDD -VinEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 13Sampling DistortioninDD thoutTV12VVinvv1eτ⎛⎞−−⎜⎟⎜⎟−⎝⎠=⎛⎞⎜⎟−⎜⎟⎜⎟⎝⎠Simulated 10-Bit ADC &Ts/2 = 5τVDD–Vth= 2V VFS= 1VSampling switch modeled:ÆResults in HD2=-41dBFS & HD3=-51.4dBFSEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 14Sampling Distortion10bit ADC Ts/2 = 10τVDD–Vth= 2V VFS= 1VDoubling sampling time (or ½time constant)Results in:HD2 improved from -41dBFS to -70dBFS ~30dBHD3 improved from -51.4dBFS to -76.3dBFS ~25dBAllowing enough time for the sampling network settling ÆReduces distortion due to switch R non-linear behavior to a tolerable levelEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 15Sampling DistortionEffect of Supply Voltage10bit ADC & Ts/2 = 5τVDD – Vth = 2V VFS= 1V• Effect of higher supply voltage on sampling distortionÆ HD3 decrease by (VDD1/VDD2)2Æ HD2 decrease by (VDD1/VDD2)10bit ADC & Ts/2 = 5τVDD–Vth= 4V VFS= 1VEECS 247- Lecture 17 Nyquist Rate ADCs-Sampling © 2008 H.K. Page 16Sampling Distortion10bit ADC Ts/τ = 20VDD–Vth= 2V VFS= 1V• SFDR Æ sensitive to sampling distortion - improve linearity by:• Larger VDD /VFS?ÆDecreased dynamic range if VDDconst.• Larger switches?Issue: Æ Increased switchcharge injectionÆ Increased nonlinear S &D junction cap.• Complementary switch• Constant & max.
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