EE247 Lecture 21 ADC Converters Techniques to reduce flash ADC complexity continued Interpolating folding continued Multi Step ADCs Two Step flash Pipelined ADCs Effect of sub ADC sub DAC gain stage non idealities on overall ADC performance Error correction by adding redundancy Digital calibration Correction for inter stage gain nonlinearity EECS 247 Lecture 21 Pipelined ADCs 2009 Page 1 Parallel Folders Using Only Zero Crossings Vin Folder 4 Comparator Vref 3 4 Folder 3 Comparator Vref 2 4 Logic LSB bits to be combined with MSB bits Folder 2 Comparator Vref 1 4 Folder 1 Comparator Vref 0 4 EECS 247 Lecture 21 Pipelined ADCs 2009 Page 2 Parallel Folder Outputs F1 F2 F3 F4 Folder Output 0 4 4 folders with 4 folds each 16 zero crossings 4 LSB bits 0 2 0 Higher resolution More folders 0 2 Large complexity 0 4 0 Interpolation 1 2 Vin 3 EECS 247 Lecture 21 4 5 Pipelined ADCs 2009 Page 3 Folding Interpolation Folder 4 Vref 3 4 Folder 3 Vref 2 4 Folder 2 Fine Flash ADC Vref 1 4 E N C O D E R Folder 1 Vref 0 4 EECS 247 Lecture 21 Pipelined ADCs 2009 Page 4 Folder Interpolator Output Example 4 Folders 4 Resistive Interpolator per Stage Folder Interpolator Output 0 5 F1 F2 I1 I2 I3 0 4 0 3 0 04 0 2 0 02 0 1 0 0 0 02 0 1 1 5 0 2 0 3 0 4 0 5 0 1 EECS 247 Lecture 21 2 3 Vin 4 5 Pipelined ADCs 1 6 1 7 1 8 Note Output of two folders only corresponding interpolator only shown 2009 Page 5 A 70 MS s 110 mW 8 b CMOS Folding and Interpolating A D Converter Ref B Nauta and G Venes JSSC Dec 1985 pp 1302 8 EECS 247 Lecture 21 Pipelined ADCs 2009 Page 6 A 70 MS s 110 mW 8 b CMOS Folding and Interpolating A D Converter Note Total of 40 MSB 8 LSB 32 comparators compared to 28 1 255 for straight flash EECS 247 Lecture 21 Pipelined ADCs 2009 Page 7 A 70 MS s 110 mW 8 b CMOS Folding and Interpolating A D Converter Ref B Nauta and G Venes JSSC Dec 1985 pp 1302 8 EECS 247 Lecture 21 Pipelined ADCs 2009 Page 8 Multi Step ADCs Two Step flash Pipelined ADCs Effect of sub ADC sub DAC gain stage non idealities on overall ADC performance Error correction by adding redundancy Digital calibration Correction for inter stage gain nonlinearity Implementation Practical circuits Stage scaling Combining the bits Stage implementation Circuits Noise budgeting How many bits per stage EECS 247 Lecture 21 Pipelined ADCs 2009 Page 9 Two Step Example 2 2 Bits 2 bit ADC Dout 11 2 bit ADC Vin Vin 10 01 00 1 Dout Vin q1 0 1 2 3 0 5 q1 LSB 0 0 5 1 0 1 2 3 ADC Input LSB Using only one ADC output contains large quantization error Missing voltage or residue q1 Idea Use second ADC to quantize and add q1 EECS 247 Lecture 21 Pipelined ADCs 2009 Page 10 Two Stage Example Vref2 Vref1 Vin Coarse q1 Fine 2 bit DAC 2 bit ADC 2 bit ADC q1 q2 Dout Vin q1 q1 q2 Use DAC to compute missing voltage Add quantized representation of missing voltage Why does this help How about q2 Since maximum voltage at input of the 2nd ADC is Vref1 4 then for 2nd ADC Vref2 Vref1 4 and thus q2 q1 4 Vref1 16 4bit overall resolution EECS 247 Lecture 21 Pipelined ADCs 2009 Page 11 Two Step 2 2 Flash ADC 4 bit Straight Flash ADC Vin Ideal 2 step Flash ADC Vin Vin Voltage quantized by 2nd ADC EECS 247 Lecture 21 Pipelined ADCs 2009 Page 12 Two Stage Example q1 11 V ref1 10 22 Vref1 Vin 01 V ref2 Second ADC Fine 00 00 01 10 11 First ADC Coarse Fine ADC is re used 22 times Fine ADC s full scale range needs to span only 1 LSB of coarse quantizer q2 EECS 247 Lecture 21 Vref 2 2 2 Vref 1 22 22 Pipelined ADCs 2009 Page 13 Two Stage 2 2 ADC Transfer Function Dout 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Coarse Bits MSB EECS 247 Lecture 21 Vref1 Fine Bits LSB Pipelined ADCs Vin 2009 Page 14 Coarse ADC B1 Bit DAC B1 Bit Residue Fine ADC B2 Bit optional B1 B2 Bit Vin Bit Combiner Residue or Multi Step Type ADC Issues Operation Coarse ADC determines MSBs DAC converts the coarse ADC output to analog Residue is found by subtracting Vin VDAC Fine ADC converts the residue and determines the LSBs Bits are combined in digital domain Issue 1 Fine ADC has to have precision in the order of overall ADC 1 2LSB 2 Speed penalty Need at least 1 clock cycle per extra series stage to resolve one sample EECS 247 Lecture 21 Pipelined ADCs 2009 Page 15 Solution to Issue 1 Reducing Precision Required for Fine ADC 2 bit ADC Vin 2 bit DAC Coarse q1 G 2B1 2 bit ADC Fine q1 q2 Dout Vin q1 q1 q2 Accuracy needed for fine ADC relaxed by introducing inter stage gain Example By adding gain of x G 2B1 4 prior to fine ADC in 2 2 bit case precision required for fine ADC is reduced to 2 bit only Additional advantage coarse and fine ADC can be identical stages EECS 247 Lecture 21 Pipelined ADCs 2009 Page 16 Solution to Issue 2 Increasing ADC Throughput 2 bit ADC Vin T H G 2B1 2 bit DAC Coarse q1 Fine T H Dout Vin 2 bit ADC q1 q1 q2 Conversion time significantly decreased by employing T H between stages All stages busy at all times operation concurrent During one clock cycle coarse fine ADCs operate concurrently First stage samples converts generates residue of input signal sample n While 2nd samples converts residue associated with sample n 1 EECS 247 Lecture 21 Pipelined ADCs 2009 Page 17 Multi Step ADCs Two Step flash Pipelined ADCs Effect of sub ADC sub DAC gain stage non idealities on overall ADC performance Error correction by adding redundancy Digital calibration Correction for inter stage gain nonlinearity Implementation Practical circuits Stage scaling Combining the bits Stage implementation Circuits Noise budgeting How many bits per stage EECS 247 Lecture 21 Pipelined ADCs 2009 Page 18 Pipeline ADC Block Diagram Vin Stage 1 B1 Bits Vres1 Stage 2 B2 Bits Vres2 MSB Stage k Bk Bits LSB Align and Combine Data Digital output B1 B2 Bk Bits Idea Cascade several low resolution stages to obtain high overall resolution e g 10bit ADC can be built with series of 10 ADCs each 1 bit only Each stage performs coarse A D conversion and computes its quantization error or residue All stages operate concurrently EECS 247 Lecture 21 Pipelined ADCs 2009 Page 19 Pipeline ADC Characteristics Number of components stages grows linearly with resolution Pipelining Trading latency for conversion speed Latency …
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