EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 1EE247Lecture 21ADC Converters–Techniques to reduce flash ADC complexity (continued)• Interpolating & folding (continued)–Multi-Step ADCs• Two-Step flash• Pipelined ADCs– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall ADC performance• Error correction by adding redundancy• Digital calibration• Correction for inter-stage gain nonlinearityEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 2Parallel Folders Using Only Zero-CrossingsVref+ 3/4 * ΔComparatorFolder 3Folder 2Folder 1Folder 4LogicVref+ 2/4 * ΔVref+ 1/4 * ΔVref+ 0/4 * ΔVinLSB bits(to be combined with MSB bits)ComparatorComparatorComparatorEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 3Parallel Folder Outputs• 4 folders with 4 folds each• 16 zero crossings• 4 LSB bits• Higher resolution• More folders Large complexity• Interpolation0 1 2 3 4 5-0.4-0.200.20.4Vin /Δ Folder OutputF1F2F3F4EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 4Folding & InterpolationFineFlashADCENCODERVref+ 3/4 * ΔFolder 3Folder 2Folder 1Folder 4Vref+ 2/4 * ΔVref+ 1/4 * ΔVref+ 0/4 * ΔEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 5Folder / Interpolator OutputExample:4 Folders + 4 Resistive Interpolator per Stage0 1 2 3 5-0.5-0.4-0.3-0.2-0.100.10.20.30.40.5Vin / ΔFolder / Interpolator OutputF1F2I1I2I31.5 1.6 1.7 1.8-0.0200.020.044Note: Output of two folders only + corresponding interpolator only shownEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 6A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D ConverterRef: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 7A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D ConverterNote: Total of 40 (MSB=8, LSB=32) comparators compared to 28-1= 255 for straight flashEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 8A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D ConverterRef: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 9Multi-Step ADCs• Two-Step flash• Pipelined ADCs– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall ADC performance• Error correction by adding redundancy• Digital calibration• Correction for inter-stage gain nonlinearity– Implementation • Practical circuits• Stage scaling• Combining the bits• Stage implementation– Circuits– Noise budgeting• How many bits per stage?EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 10Two-Step Example: (2+2)Bits• Using only one ADC: output contains large quantization error• "Missing voltage" or "residue" ( -εq1)• Idea: Use second ADC to quantize and add -εq10 1 2 3000110110 1 2 3-1-0.500.51[LSB]ADC Input [LSB]Vin+Dout= Vin + εq12-bit ADC 2-bit ADC???εq1DoutVinEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 11Two Stage Example• Use DAC to compute missing voltage• Add quantized representation of missing voltage• Why does this help? How about εq2? • Since maximum voltage at input of the 2ndADC is Vref1/4 then for 2ndADC Vref2=Vref1/4 and thus εq2= εq1/4 =Vref1/16 4bit overall resolutionVin“Coarse“+Dout= Vin+ εq1 2-bit ADC 2-bit ADC“Fine“+-2-bit DAC-εq1-εq1+εq2-εq1+εq2Vref2Vref1EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 12Two Step (2+2) Flash ADCVinVinVin4-bit Straight Flash ADC Ideal 2-step Flash ADCVoltage quantized by 2ndADCEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 13Two Stage Example• Fine ADC is re-used 22times• Fine ADC's full scale range needs to span only 1 LSB of coarse quantizer221222222 ⋅==refrefqVVε00 01 10 11Vref1/22−εq100011011First ADC“Coarse“Second ADC“Fine“VinVref1Vref2EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 14Two-Stage (2+2) ADC Transfer Function0000000100100011010001010110011110001001101010111100110111101111CoarseBits(MSB)FineBits(LSB)DoutVinVref1EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 15Residue or Multi-Step Type ADCIssues• Operation:– Coarse ADC determines MSBs– DAC converts the coarse ADC output to analog- Residue is found by subtracting (Vin-VDAC)– Fine ADC converts the residue and determines the LSBs– Bits are combined in digital domain • Issue: 1. Fine ADC has to have precision in the order of overall ADC 1/2LSB 2. Speed penalty Need at least 1 clock cycle per extra series stage to resolve one sample (optional)Coarse ADC(B1-Bit)VinResidueDAC(B1-Bit)Fine ADC(B2-Bit)Bit Combiner(B1+B2)-BitEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 16Solution to Issue (1)Reducing Precision Required for Fine ADC• Accuracy needed for fine ADC relaxed by introducing inter-stage gain– Example: By adding gain of x(G=2B1=4) prior to fine ADC in (2+2)bit case, precision required for fine ADC is reduced to 2-bit only!– Additional advantage- coarse and fine ADC can be identical stagesVin“Coarse“+Dout= Vin+ εq1 2-bit ADC 2-bit ADC“Fine“+-2-bit DAC-εq1-εq1+εq2-εq1+εq2G=2B1EECS 247- Lecture 21 Pipelined ADCs © 2009 Page 17Solution to Issue (2)Increasing ADC Throughput• Conversion time significantly decreased by employing T/H betweenstages– All stages busy at all times operation concurrent– During one clock cycle coarse & fine ADCs operate concurrently:• First stage samples/converts/generates residue of input signal sample # n• While 2ndsamples/converts residue associated with sample # n-1Vin“Coarse“+Dout= Vin+ εq1 2-bit ADC2-bit ADC“Fine“+-2-bit DAC-εq1-εq1+εq2T/H+(G=2B1)T/HEECS 247- Lecture 21 Pipelined ADCs © 2009 Page 18Multi-Step ADCs• Two-Step flash• Pipelined ADCs– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall ADC performance• Error correction by adding redundancy• Digital calibration• Correction for inter-stage gain nonlinearity– Implementation • Practical circuits•
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