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Berkeley ELENG 247A - Lecture Notes

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EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 1EE247Lecture 21ADC Converters– Comparator design • Single-stage open-loop amplifier• Cascade of open-loop amplifiers• Problem associated with DC offset– Cascaded output series cancellation– Input series cancellation– Offset cancellation through additional input pair plus offset storage capacitors• Latched comparators• Comparator examplesEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 2Summary Last LectureADC Converters– Sampling (continued)• Effect of clock jitter on sampling– ADC architectures and design • Serial- slope type• Successive approximation•Flash• Flash ADC sources of error– Comparator offset– Sparkle code– Meta-stabilityEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 3Voltage ComparatorsPlay an important role in majority of ADCsFunction: Compare the instantaneous value of two analog signals & generate a digital output voltage based on the sign of the difference:+-Vout (Digital Output)VDD If Vi+-Vi-> 0 ÆVout=“1”If Vi+-Vi-< 0 ÆVout=“0”Vi+Vi-EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 4Voltage ComparatorArchitecturesComparator architectures:• High gain amplifier with differential analog input & single-ended large swing output– Output swing has to be compatible with driving digital logic circuits– Open-loop amplificationÆ no frequency compensation required– Precise gain not required• Latched comparators; in response to a strobe (clock edge), input stage disabled & digital output stored in a latch till next strobe– Two options for implementation :• Latch-only comparator• Low-gain amplifier + high-sensitivity latch• Sample-data comparators– T/H input– Offset cancellationEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 5Comparators Built with High-Gain AmplifierAmplify Vin(min) to VDD Æ Vin(min) determined by ADC resolutionExample: 12-bit ADC with:-VFS= 1.5VÆ 1LSB=0.36mV-VDD=1.8VÆ For 1.8V output & 0.5LSB precision:Minv1.8VA10,0000.18mV=≈EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 6Comparators 1-Single-Stage AmplificationToo slow for majority of applications!Æ Try cascade of lower gain stages to broaden frequency of operationfu=0.1-10GHzf0fufrequencyGainAvuouoVuVosettlingoMax.Clocksettlingfunity-gain frequency, f =-3dB frequency f f= AExample: f =10GHz & A 10,00010GHz f1MHz10,00010.16 sec2fAllowa few for output to settle 1f1.26MHz5τμπττ===≈==→≈Assumption: Single pole amplifierEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 7Comparators2- Cascade of Open Loop AmplifiersThe stages identical Æ small-signal model for the cascades:One stage:EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 8Open Loop Cascade of AmplifiersEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 9Open Loop Cascade of AmplifiersFor |AT(DC)|=10,000()uT1/3 1oN1/3settlingoMax.ClocksettlingExample: N=3, f =10GHz & A (0) 1000010GHzf2237MHz10,00010.7nsec2fAllowa few for output to settle 1f290MHz5τπττ−==≈==→≈fmaximproved from 1.26MHz to 290MHz ÆX236EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 10Open Loop Cascade of AmplifiersOffset Voltage• From offset point of view: high gain/stage is preferred• Choice of # of stage Æbandwidth vs offset tradeoffInput-referred offset ÆEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 11Open Loop Cascade of AmplifiersStep Response• Assuming linear behavior (not slew limited)tEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 12Open Loop Cascade of AmplifiersStep Response•Assuming linear behaviorEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 13Open Loop Cascade of AmplifiersDelay/(C/gm)• Minimum total delay broad function of N• Relationship between # of stages resulting in minimize delay (Nop) and gain (Vout/Vin) approximately:Delay/(C/gm)Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988. N1 log A for A 1000opt 2 TN1.2lnA for A 1000opt T≈+ <≈≥EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 14Offset Cancellation• In sampled-data cascade of amplifiers Vos can be cancelled Æ Store on ac-coupling caps in series with amp stages• Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of thatstage• Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux. inputs during offset cancellation phaseRef: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988.EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 15Offset CancellationOutput Series Cancellation• Amp modeled as ideal + Vos(input referred)• Store offset:•S1, S4Î open•S2, S3Æ closedÆ VC=AxVOSRef: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988. EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 16Offset CancellationOutput Series CancellationAmplify:• S1, S4Î closed• S2, S3Æ openÆVC=AxVOSCircuit requirements:• Amp not saturate during offset storage• High-impedance (C) load Æ Ccnot discharged• Cc>> CLto avoid attenuation• Cc>> Cswitchavoid excessive offset due to charge injectionEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 17Offset CancellationCascaded Output Series CancellationNote: Offset storage capacitors in series with the amplifier outputsEECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design © 2007 H.K. Page 18Offset CancellationCascaded Output Series Cancellation1- S1Æ open, S2,3,4,5


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Berkeley ELENG 247A - Lecture Notes

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