EE247 Lecture 21 ADC Converters Comparator design Single stage open loop amplifier Cascade of open loop amplifiers Problem associated with DC offset Cascaded output series cancellation Input series cancellation Offset cancellation through additional input pair plus offset storage capacitors Latched comparators Comparator examples EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 1 Summary Last Lecture ADC Converters Sampling continued Effect of clock jitter on sampling ADC architectures and design Serial slope type Successive approximation Flash Flash ADC sources of error Comparator offset Sparkle code Meta stability EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 2 Voltage Comparators VDD Vi Vi Vout Digital Output Play an important role in majority of ADCs Function Compare the instantaneous value of two analog signals generate a digital output voltage based on the sign of the difference If Vi Vi 0 Vout 1 If Vi Vi 0 Vout 0 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 3 Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input single ended large swing output Output swing has to be compatible with driving digital logic circuits Open loop amplification no frequency compensation required Precise gain not required Latched comparators in response to a strobe clock edge input stage disabled digital output stored in a latch till next strobe Two options for implementation Latch only comparator Low gain amplifier high sensitivity latch Sample data comparators T H input Offset cancellation EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 4 Comparators Built with High Gain Amplifier Amplify Vin min to VDD Vin min determined by ADC resolution Example 12 bit ADC with VFS 1 5V 1LSB 0 36mV VDD 1 8V For 1 8V output 0 5LSB precision Av Mi n 1 8V 0 18mV EECS 247 Lecture 21 10 000 Nyquist Rate ADC Comparator Design 2007 H K Page 5 Comparators 1 Single Stage Amplification fu unity gain fre que nc y fo 3dB frequency fo fu AV Ex am ple fu 10GHz AV 10 000 fo Gain Av 10GHz 1M Hz 10 000 1 se t tl in g 0 16 sec 2 fo A llow a fe w f or out put to se ttle 1 Max fCloc 1 26M Hz k 5 se t tl in g fu 0 1 10GHz f0 fu frequency Assumption Single pole amplifier Too slow for majority of applications Try cascade of lower gain stages to broaden frequency of operation EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 6 Comparators 2 Cascade of Open Loop Amplifiers The stages identical small signal model for the cascades One stage EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 7 Open Loop Cascade of Amplifiers EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 8 Open Loop Cascade of Amplifiers For AT DC 10 000 Example N 3 fu 10GHz AT 0 10000 foN 10GHz 10 000 1 3 settling 21 3 1 237MHz 1 0 7n sec 2 fo Allow a few for output to settle Max fClock 1 290MHz 5 settling fmax improved from 1 26MHz to 290MHz X236 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 9 Open Loop Cascade of Amplifiers Offset Voltage From offset point of view high gain stage is preferred Choice of of stage bandwidth vs offset tradeoff Input referred offset EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 10 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior not slew limited t EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 11 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 12 Open Loop Cascade of Amplifiers Delay C gm Minimum total delay broad Delay C gm function of N Relationship between of stages resulting in minimize delay Nop and gain Vout Vin approximately Nopt 1 l og2 AT f or A 1000 Nopt 1 2l n AT for A 1000 Ref J T Wu et al A 100 MHz pipelined CMOS comparator IEEE Journal of Solid State Circuits vol 23 pp 1379 1385 December 1988 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 13 Offset Cancellation In sampled data cascade of amplifiers Vos can be cancelled Store on ac coupling caps in series with amp stages Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of that stage Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux inputs during offset cancellation phase Ref J T Wu et al A 100 MHz pipelined CMOS comparator IEEE Journal of Solid State Circuits vol 23 pp 1379 1385 December 1988 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 14 Offset Cancellation Output Series Cancellation Amp modeled as ideal Vos input referred Store offset S1 S4 open S2 S3 closed VC AxVOS Ref J T Wu et al A 100 MHz pipelined CMOS comparator IEEE Journal of Solid State Circuits vol 23 pp 1379 1385 December 1988 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 15 Offset Cancellation Output Series Cancellation Amplify S1 S4 closed S2 S3 open VC AxVOS Circuit requirements Amp not saturate during offset storage High impedance C load Cc not discharged Cc CL to avoid attenuation Cc Cswitch avoid excessive offset due to charge injection EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 16 Offset Cancellation Cascaded Output Series Cancellation Note Offset storage capacitors in series with the amplifier outputs EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 17 Offset Cancellation Cascaded Output Series Cancellation 1 S1 open S2 3 4 5 closed VC1 A1xVos1 VC2 A2xVos2 VC3 A1xVos3 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 18 Offset Cancellation Cascaded Output Series Cancellation 2 S3 open first Feedthrough from S3 offset on X Switch offset 3 induced on node X Since S4 remains closed offset associated with 3 stored on C2 VX 3 VC1 A1xVos1 3 VC2 A2x Vos2 3 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 19 Offset Cancellation Cascaded Output Series Cancellation 3 S4 open Feedthrough from S4 offset on Y Switch offset 4 induces error on node Y Since S5 remains closed offset associated with 4 stored on C3 VY 4 VC2 A2x Vos2 3 4 VC3 A3x Vos3 4 EECS 247 Lecture 21 Nyquist Rate ADC Comparator Design 2007 H K Page 20 Offset Cancellation Cascaded Output Series Cancellation 4 S2 open S1 closed S5 open S1 closed S2 open since input connected to
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