EE247 Lecture 18 ADC Converters Track hold T H circuits T H combined with summing difference function T H circuit incorporating gain offset cancellation T H aperture uncertainty ADC architectures and design Serial slope type Successive approximation Flash ADC and its sources of error comparator offset sparkle code meta stability Comparator design Single stage open loop amplifier Cascade of open loop amplifiers EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 1 Summary of Last Lecture ADC Converters Sampling continued Sampling switch considerations Clock voltage boosters Sampling switch charge injection clock feedthrough Complementary switch Use of dummy device Bottom plate switching Track hold Flip around T H EECS 247 Lecture 17 Data Converters ADC Design Sampling 2010 Page 2 Flip Around T H Basic Operation f1 high f2 S2A f1 f1D f1D f2 f1D C vIN f2 S3 Charging C vOUT S2 S1A f1 Qf1 VINxC S1 vCM EECS 247 Lecture 17 Note Opamp has to be stable in unity gain configuration Data Converters Track Hold ADC Design 2009 Page 3 Flip Around T H Basic Operation f2 high f2 S2A f1 f1D f1D f2 f1D vIN C f2 S3 vOUT S2 S1A f1 S1 vCM EECS 247 Lecture 17 Holding Qf2 VOUT xC VOUT VIN Data Converters Track Hold ADC Design 2009 Page 4 Differential Flip Around T H S11 S12 Offset voltage associated with charge injection of S11 S12 cancelled by differential nature of the circuit Ref W Yang et al A 3 V 340 mW 14 b 75 Msample s CMOS ADC With 85 dB SFDR at Nyquist Input IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 12 DECEMBER 2001 1931 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 5 Differential Flip Around T H f1 f1 f2 Gain 1 Issue Large input common mode compliance required EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 6 Differential Flip Around T H Issues Large Input Common Mode Compliance 1 7V 1V VCMVin 1 5V 0 5V 1 2V 0 5V 0 8V 1V 1V 1 3V DVin cm 1 1 5 0 5V DVin cm Vout com Vsig com Drawback Amplifier needs to have large input common mode compliance EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 7 Input Common Mode Cancellation Note Shorting switch M3 added Ref R Yen et al A MOS Switched Capacitor Instrumentation Amplifier IEEE JOURNAL OF SOLID STATE CIRCUITS VOL SC 17 NO 6 DECEMBER 1982 1008 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 8 Input Common Mode Cancellation 1V 0 2V 0 1 1 2 0 1 0 1 0 1 1V 0 2V 0 8 Track mode f high VC1 VI1 VC2 VI2 Vo1 Vo2 0 Hold mode f low Vo1 Vo2 0 Vo1 Vo2 VI1 VI2 C1 C1 C3 Input common mode level removed Will introduce active version in page 18 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 9 Switched Capacitor Techniques Combining Track Hold with Various other Functions T H Charge redistribution amplifier T H Input difference amplifier T H summing amplifier Differential T H combined with gain stage Differential T H including offset cancellation EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 10 T H Charge Redistribution Amplifier S3 on S2 off VC1 Vos VIN VC2 0 Vo Vos Track mode S1 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 11 T H Charge Redistribution Amplifier Hold Mode 22 1 Hold amplify mode S1 S3 off S2 on Offset NOT cancelled but not amplified Input referred offset C2 C1 x VOS often C2 C1 Can incorporate gain by having C1 C2 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 12 T H Input Difference Amplifier Sample mode S1 S3 on S2 off VC1 Vos VI1 VC2 0 Vo Vos EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 13 Input Difference Amplifier Cont d Subtract Amplify mode S1 S3 off S2 on During previous phase VC1 Vos VI1 VC2 0 Vo Vos 1 Offset NOT cancelled but not amplified Input referred offset C2 C1 xVOS C2 C1 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 14 T H Summing Amplifier EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 15 T H Summing Amplifier Cont d Sample mode S1 S3 S5 on S2 S4 off VC1 Vos VI1 VC2 Vos VI3 VC3 0 Vo Vos EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 16 T H Summing Amplifier Cont d Amplify mode S1 S3 S5 off S2 S4 on 3 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 17 Differential T H Combined with Gain Stage Employs the previously discussed technique to eliminate the problem associated with high common mode voltage excursion at the input of the opamp Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 18 Differential T H Combined with Gain Stage f1 High Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 19 Differential T H Combined with Gain Stage Gain 4C C 4 Input voltage common mode level removed opamp can have low input common mode compliance Amplifier offset NOT removed Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 20 Differential T H Including Offset Cancellation Operation during offset cancellation phase shown Auxiliary inputs added with Amain Aaux 10 During offset cancellation phase Aux amp configured in unity gain mode offset stored on CAZ canceled during the signal acquisition phase Ref H Ohara et al A CMOS programmable self calibrating 13 bit eight channel data acquisition peripheral IEEE Journal of Solid State Circuits vol 22 pp 930 938 December 1987 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 21 Differential T H Including Offset Cancellation Operational Amplifier Operational amplifier dual input folded cascode opamp M3 4 auxiliary input M1 2 main input To achieve 1 10 gain ratio WM3 4 1 10x WM1 2 current sources are scaled by 1 10 M5 6 7 common mode control Output stage dual cascode high DC gain Vout gm1 2roVin1 gm3 4roVin2 Ref H Ohara et al A CMOS programmable self calibrating 13 bit eight channel data acquisition peripheral IEEE Journal of Solid State Circuits vol 22 pp 930 938 December 1987 EECS 247 Lecture 18 Data Converters Track Hold ADC Design 2010 Page 22 Differential T H Including Offset Cancellation Phase VINAZ VINAZ gm1 2 gm3 4Voffset Voffset During offset cancellation phase AZ and S1 closed main …
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