EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 1EE247Lecture 18ADC Converters– Track & hold • T/H circuits• T/H combined with summing/difference function• T/H circuit incorporating gain & offset cancellation• T/H aperture uncertainty– ADC architectures and design • Serial- slope type• Successive approximation• Flash ADC and its sources of error: comparator offset, sparkle code & meta-stability– Comparator design • Single-stage open-loop amplifier• Cascade of open-loop amplifiersEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2010 Page 2Summary of Last LectureADC Converters– Sampling (continued)• Sampling switch considerations– Clock voltage boosters• Sampling switch charge injection & clock feedthrough– Complementary switch– Use of dummy device– Bottom-plate switching– Track & hold • Flip around T/HEECS 247 Lecture 17: Data Converters- Track & Hold- ADC Design © 2009 Page 3Flip-Around T/H-Basic Operationf1highvINvOUTCS1Af1DS2f2S2Af2S3f1Df1S1vCMCharging Cf1f1Df2Note: Opamp has to be stable in unity-gain configurationQf1=VINxCEECS 247 Lecture 17: Data Converters- Track & Hold- ADC Design © 2009 Page 4Flip-Around T/H-Basic Operationf2highvINvOUTCS1Af1DS2f2S2Af2S3f1Df1S1vCMHoldingf1f2f1DQf2=VOUT xCVOUT = VINEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 5Differential Flip-Around T/HRef: W. Yang, et al. “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931Offset voltage associated with charge injection of S11 & S12 cancelled by differential nature of the circuitS11S12EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 6Differential Flip-Around T/H• Gain=1• Issue: Large input common-mode compliance requiredf1’f1f2EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 7Differential Flip-Around T/HIssues: Large Input Common-Mode Compliance• DVin-cm=Vout_com-Vsig_com Drawback: Amplifier needs to have large input common-mode complianceVCMVin=1.5V1.7V1.3V1V1V1V1.2V0.8V0.5VDVin-cm=1-1.5= - 0.5V0.5VEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 8Input Common-Mode CancellationRef: R. Yen, et al. “A MOS Switched-Capacitor Instrumentation Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008• Note: Shorting switch M3 addedEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 9Input Common-Mode CancellationTrack mode (f high)VC1=VI1, VC2=VI2Vo1=Vo2=0Hold mode (f low)Vo1+Vo2=0Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3))Input common-mode level removed• Will introduce active version in page 18 1V+0.2V1V-0.2V+ 1.2 -+ 0.8 -+ 0.1 -- 0.1 ++0.1--0.1+EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 10Switched-Capacitor Techniques Combining Track & Hold with Various other Functions • T/H + Charge redistribution amplifier• T/H & Input difference amplifier• T/H & summing amplifier• Differential T/H combined with gain stage• Differential T/H including offset cancellationEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 11T/H + Charge Redistribution AmplifierTrack mode: (S1, S3 on S2 off)VC1=Vos–VIN, VC2=0Vo=VosEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 12T/H + Charge Redistribution AmplifierHold ModeHold/amplify mode (S1, S3 off S2 on) Offset NOT cancelled, but not amplified Input-referred offset =(C2/C1) x VOS, & often C2<C1 Can incorporate gain by having C1>C2212EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 13T/H & Input Difference AmplifierSample mode:(S1, S3 on S2 off)VC1=Vos–VI1, VC2=0Vo=VosEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 14Input Difference AmplifierCont„dSubtract/Amplify mode (S1, S3 off S2 on)During previous phase:VC1=Vos–VI1, VC2=0Vo=Vos1Offset NOT cancelled, but not amplifiedInput-referred offset =(C2/C1)xVOS, & C2<C1EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 15T/H & Summing AmplifierEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 16T/H & Summing AmplifierCont„dSample mode (S1, S3, S5on S2, S4 off)VC1=Vos–VI1, VC2=Vos-VI3, VC3=0Vo=VosEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 17T/H & Summing AmplifierCont„dAmplify mode (S1, S3, S5off, S2, S4 on)3EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 18Differential T/H Combined with Gain StageRef: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opampEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 19Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987Differential T/H Combined with Gain Stagef1 HighEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 20Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987• Gain=4C/C=4• Input voltage common-mode level removed opamp can have low input common-mode compliance• Amplifier offset NOT removedDifferential T/H Combined with Gain StageEECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design © 2010 Page 21Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987. • Operation during offset cancellation phase shown• Auxiliary inputs added with Amain/Aaux.=10• During offset
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