EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 1EE247Lecture 14• D/A converters continued:– Resistor string DACs (continued)– Serial charge redistribution DACs– Charge scaling DACs– R-2R type DACs– Current based DACs– Static performance of D/As• Component matching• Systematic & random errors– Practical aspects of current-switched DACs– Segmented current-switched DACsEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 2R-String DAC• Advantages:– Takes full advantage of availability of almost perfect switches in MOS technologies– Simple, fast for <8-10bits– Inherently monotonic– Compatible with purely digital technologies• Disadvantages:–2Bresistors & ~2x2Bswitches for B bits Æ High element count & large area for B >10bits– High settling time for high resolution DACs:τmax~ 0.25 x 2BRCCRef:M. Pelgrom, “A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer,” JSSC, Dec. 1990, pp. 1347VrefEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 3R-String DACIncluding InterpolationResistor string DAC + Resistor string interpolator increases resolution w/o drastic increase in complexitye.g. 10bit DACÆ (5bit +5bitÆ 2x25=26 # of Rs) instead of direct 10bitÆ210 Considerations:Main R-string loaded by the interpolation string resistorsLarge R values for interpolating stringÆless loading but lower speedCan use buffersVoutVrefEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 4R-String DACIncluding InterpolationUse buffers to prevent loading of the main ladderIssues: Æ Buffer DC offset Æ Effect of buffer bandwidth limitations on overall speedVrefEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 5Charge Based: Serial Charge Redistribution DACSimplified Operation• Operation based on redistribution of charge associated with C1 &C2 to perform accurate division by factor of 2Nominally C1=C2EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 6Charge Based: Serial Charge Redistribution DACSimplified Operation: Conversion Sequence()()12 1 2T1 T1 T2 T2CC C C 12REF 1 1 21REF12REF12ooooQQ QQ CCVVCCCVCVVCCVSince C C V2++=+×= +=×+=→==T1T21112T1 T1C REF 1 CT1 T1C C REF 1QV C& Q0QQV C×→+= ×==EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 7• Conversion sequence:– Next cycle • If S3 closed VC1=0 then when S1 closes VC1 = VC2 = VREF/4• If S2 closed VC1=VREFthen when S1 closes VC1 =VC2 =VREF/2+VREF/4Serial Charge Redistribution DACSimplified Operation (Cont’d)T1T2EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 8Serial Charge Redistribution DAC• Conversion sequence:– Discharge C1 & C2Æ S3& S4 closed– For each bit in succession beginning with LSB, b1:• S1 open- if bi=1 C1 precharge to VREFif bi=0 discharged to GND• S2 & S3 & S4 open- S1 closed- Charge sharing C1 & C2Æ ½ of precharge on C1 +½ of charge previously stored on C2Æ C2EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 9Serial Charge Redistribution DACExample: Input Code 101b3b2b1LSBMSB• Example input code 101Æ output (4/8 +0/8 +1/8 )VREF=5/8 VREF• Very small area• For an N-bit DAC, N redistribution cycles for one full analog output generation Æ quite slowEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 10Parallel Charge Scaling DACÆ Make Cx & Cy function of incoming DAC digital wordVrefVoutCCxCyoutrefCxVVCx Cy C+=+• DAC operation based on capacitive voltage divisionEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 11Parallel Charge Scaling DAC• E.g. “Binary weighted”• B+1 capacitors & switches (Cs built of unit elements Æ 2Bunits of C)CC2C4C8C2(B-1)CVrefVoutresetb0(lsb)b1b2b3bB-1(msb)B1iii0outrefBb2CVV2C−==∑EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 12Charge Scaling DACExample: 4Bit DAC- Input Code 1011CC2C4C8CVrefVoutb0(lsb)b1b2b3CC2C4C8CVrefVoutresetb0(lsb)b1b2b32- Charge phase1- Reset phase013outref ref42C 2C 2C 11VVV2C 16=++=EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 13Charge Scaling DAC• Sensitive to parasitic capacitor @ output– If Cpconstant Æ gain error– If Cpvoltage dependant Æ DAC nonlinearity• Large area of caps for high DAC resolution (10bit DAC ratio 1:512)• Monotonicity depends on element matching (more later)refPBBiiioutVCCCbV+=∑−=2210CC2C4C8C2(B-1)CVrefVoutresetb0(lsb)b1b2b3bB-1(msb)CPEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 14Parasitic InsensitiveCharge Scaling DAC• Opamp helps eliminate the parasitic capacitor effect by producing virtual ground at the sensitive node since CPhas zero volts at start & end – Issue: opamp offset & speedC2C4C8C2(B-1)CVrefVoutresetb0(lsb)b1b2b3bB-1(msb)CPCI-+CIB1 B1iib2C b2iiBi0 i0VV,C2CVVout ref I out refBC2I−−∑∑===− = → =−EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 15Charge Scaling DACIncorporating Offset Compensation• During reset phase:– Opamp disconnected from capacitor array via switch S3– Opamp connected in unity-gain configuration (S1)– CIBottom plate connected to ground (S2)– Vout ~ - VosÆVCI = -Vos• This effectively compensates for offset during normal phaseC2C4C8C2(B-1)CVrefVoutresetb0(lsb)b1b2b3bB-1(msb)CP-+CIosVresetresetS1S2S3EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 16Charge Scaling DACUtilizing Split Array• Split arrayÆ reduce the total area of the capacitors required for high resolution DACs– E.g. 10bit regular binary array requires 1024 unit Cs while split array (5&5) needs 64 unit Cs– Issue: Sensitive to parasitic capacitorseriesall LSB array CCCall MSB arrayC=∑∑C2C4CVrefVoutresetb5b4b3b2+-8/7CC2C4Cb1b0CEECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 17Charge Scaling DAC• Advantages:– Low power dissipation Æ capacitor array does not dissipate DC power– Output is sample and held Æ no need for additional S/H– INL function of
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