EE247 Lecture 14 D A converters continued Resistor string DACs continued Serial charge redistribution DACs Charge scaling DACs R 2R type DACs Current based DACs Static performance of D As Component matching Systematic random errors Practical aspects of current switched DACs Segmented current switched DACs EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 1 R String DAC Advantages Takes full advantage of availability of almost perfect switches in MOS technologies Simple fast for 8 10bits Inherently monotonic Compatible with purely digital technologies Vref Disadvantages 2B resistors 2x2B switches for B bits High element count large area for B 10bits High settling time for high resolution DACs max 0 25 x 2B RC C Ref M Pelgrom A 10 b 50 MHz CMOS D A Converter with 75 W Buffer JSSC Dec 1990 pp 1347 EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 2 R String DAC Including Interpolation Resistor string DAC Resistor string interpolator increases resolution w o drastic increase in complexity e g 10bit DAC 5bit 5bit 2x25 26 of Rs instead of direct 10bit 210 Vref Considerations Vout Main R string loaded by the interpolation string resistors Large R values for interpolating string less loading but lower speed Can use buffers EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 3 R String DAC Including Interpolation Use buffers to prevent loading of the main ladder Vref Issues Buffer DC offset Effect of buffer bandwidth limitations on overall speed EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 4 Charge Based Serial Charge Redistribution DAC Simplified Operation Nominally C1 C2 Operation based on redistribution of charge associated with C1 C2 to perform accurate division by factor of 2 EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 5 Charge Based Serial Charge Redistribution DAC Simplified Operation Conversion Sequence T2 T1 QCT11 VREF C1 QCT11 QCT12 VREF C1 QCT11 0 QCT11 QCT12 QCT 2 QCT 2 C1 C2 Vo 1 VREF C1 C1 C2 Vo Vo VREF C1 C1 C2 S i nce C1 C2 EECS 247 Lecture 14 2 Data Converters DAC Design Vo VREF 2 2008 H K Page 6 Serial Charge Redistribution DAC Simplified Operation Cont d T2 T1 Conversion sequence Next cycle If S3 closed VC1 0 then when S1 closes VC1 VC2 VREF 4 If S2 closed VC1 VREF then when S1 closes VC1 VC2 VREF 2 VREF 4 EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 7 Serial Charge Redistribution DAC Conversion sequence Discharge C1 C2 S3 S4 closed For each bit in succession beginning with LSB b1 S1 open if bi 1 C1 precharge to VREF if bi 0 discharged to GND S2 S3 S4 open S1 closed Charge sharing C1 C2 of precharge on C1 of charge previously stored on C2 C2 EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 8 Serial Charge Redistribution DAC Example Input Code 101 LSB b3 b2 MSB b1 Example input code 101 output 4 8 0 8 1 8 VREF 5 8 VREF Very small area For an N bit DAC N redistribution cycles for one full analog output generation quite slow EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 9 Parallel Charge Scaling DAC DAC operation based on capacitive voltage division Vout Cy Cx C Vout Cx Vref Cx Cy C Vref Make Cx Cy function of incoming DAC digital word EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 10 Parallel Charge Scaling DAC reset Vout 2 B 1 C 8C 4C 2C C C bB 1 msb b3 b2 b1 b0 lsb Vref B 1 E g Binary weighted Vout B 1 capacitors switches Cs built of unit elements 2B units of C EECS 247 Lecture 14 bi 2 i C i 0 2B C Data Converters DAC Design Vref 2008 H K Page 11 Charge Scaling DAC Example 4Bit DAC Input Code 1011 reset 2 Charge phase 1 Reset phase Vout Vout 8C 4C 2C b3 b2 b1 C C 8C 4C b3 b2 b0 lsb Vref Vout EECS 247 Lecture 14 2C C C b1 b0 lsb Vref 20 C 21 C 23C 11 Vref Vref 24 C 16 Data Converters DAC Design 2008 H K Page 12 Charge Scaling DAC reset CP 2 B 1 C 8C bB 1 msb 4C b3 2C b2 C b1 C b0 lsb Vout B 1 Vout b 2 C i i i 0 2 B C CP Vref Vref Sensitive to parasitic capacitor output If Cp constant gain error If Cp voltage dependant DAC nonlinearity Large area of caps for high DAC resolution 10bit DAC ratio 1 512 Monotonicity depends on element matching more later EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 13 Parasitic Insensitive Charge Scaling DAC reset CI CP 2 B 1 C 8C 4C 2C C bB 1 msb b3 b2 b1 b0 lsb Vout Vref B 1 i bi 2 C Vout i 0 Vref CI B 1 i bi 2 B CI 2 C Vo ut i 0 Vref 2B Opamp helps eliminate the parasitic capacitor effect by producing virtual ground at the sensitive node since CP has zero volts at start end Issue opamp offset speed EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 14 Charge Scaling DAC Incorporating Offset Compensation CI S2 reset reset CP S3 reset 2 B 1 C 8C 4C 2C C bB 1 msb b3 b2 b1 b0 lsb S1 Vos Vout Vref During reset phase Opamp disconnected from capacitor array via switch S3 Opamp connected in unity gain configuration S1 CI Bottom plate connected to ground S2 Vout Vos VCI Vos This effectively compensates for offset during normal phase EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 15 Charge Scaling DAC Utilizing Split Array reset C 8 7C C 2C 4C b0 b1 b2 C 2C 4C b3 b4 b5 Cse rie s all LSB arra y C a ll MS B a rr ay C Vout Vref C Split array reduce the total area of the capacitors required for high resolution DACs E g 10bit regular binary array requires 1024 unit Cs while split array 5 5 needs 64 unit Cs Issue Sensitive to parasitic capacitor EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 16 Charge Scaling DAC Advantages Low power dissipation capacitor array does not dissipate DC power Output is sample and held no need for additional S H INL function of capacitor ratio Possible to trim or calibrate for improved INL Offset cancellation almost for free Disadvantages Process needs to include good capacitive material not compatible with standard digital process Requires large capacitor ratios Not inherently monotonic more later EECS 247 Lecture 14 Data Converters DAC Design 2008 H K Page 17 Segmented DAC Resistor Ladder MSB Binary Weighted Charge Scaling LSB Example 12bit DAC 6 bit MSB DAC R string 6 bit LSB DAC binary weighted charge scaling Complexity much lower compared to reset Vout 32 C 16C …
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