EE247 Lecture 25 Oversampled ADCs continued Higher order modulators Last lecture Cascaded modulators MASH continued Single loop single quantizer modulators with multi order filtering in the forward path Example 5th order Lowpass Modeling Noise shaping Effect of various nonidealities on the performance Bandpass modulators EECS 247 Lecture 25 Oversampled ADCs 2009 Page 1 EE247 Lecture 25 Administrative Final exam Date Mon Dec 14th Time 1 30pm 4 30pm note change of time Location 299 Cory change of location Closed book course notes No calculators cell phones PDAs Computers You can bring two 8x11 paper with your own notes Final exam covers the entire course material unless specified EECS 247 Lecture 25 Oversampled ADCs 2009 Page 2 EE247 Lecture 25 Project Project reports due Dec 4th Dec 2nd if you are presenting on Dec 3rd Please make an appointment with the instructor for a 20 minute meeting per team for Frid Dec 4th for early presenters Dec 2nd Prepare to give a 5 to 10 minute presentation regarding the project during the class period on Dec 8th or Dec 3rd Highlight the important aspects of your approach towards the implementation of the ADC If the project is joint effort both team members should present Email your PowerPoint presentation files to H K two hours prior to class to conserve class time EECS 247 Lecture 25 Oversampled ADCs 2009 Page 3 EE247 Lecture 25 Homework for oversampled data converters Due to the time consuming nature of the project homework covering oversampled converters will not be given Please review relevant previous year homeworks solutions e g http wwwinst eecs berkeley edu ee247 fa07 files07 homew ork HW9 2 07 pdf http wwwinst eecs berkeley edu ee247 fa07 files07 homew ork HW9 sol Lynn Wang pdf EECS 247 Lecture 25 Oversampled ADCs 2009 Page 4 Example 2 1 Cascaded Modulators Accuracy of 3 2dB loss in DR Ref L A Williams III and B A Wooley A third order sigma delta modulator with extended dynamic range IEEE Journal of Solid State Circuits vol 29 pp 193 202 March 1994 EECS 247 Lecture 25 Oversampled ADCs 2009 Page 5 2 1 Cascaded Modulators Effect of gain parameters on signal to noise ratio Ref L A Williams III and B A Wooley A third order sigma delta modulator with extended dynamic range IEEE Journal of Solid State Circuits vol 29 pp 193 202 March 1994 EECS 247 Lecture 25 Oversampled ADCs 2009 Page 6 2 1 Cascaded Modulators Measured Dynamic Range Versus Oversampling Ratio Theoretical SQNR 21dB Octave 3dB Octave Ref L A Williams III and B A Wooley A third order sigma delta modulator with extended dynamic range IEEE Journal of Solid State Circuits vol 29 pp 193 202 March 1994 EECS 247 Lecture 25 Oversampled ADCs 2009 Page 7 Comparison of 2nd order Cascaded 2 1 Modulator Test Results Digital Audio Application fN 44 1kHz Does not include Decimator Reference Brandt JSSC 4 91 Williams JSSC 3 94 Architecture 2nd order 2 1 Order Dynamic Range 98dB 16 bits 104dB 17 bits Peak SNDR 94dB 98dB Oversampling rate 256 theoretical SQNR 109dB 18bit 128 theoretical SQNR 128dB 21bit Differential input range 4Vppd 5V supply 8Vppd 5V supply Power Dissipation 13 8mW 47 2mW Active Area 0 39mm2 1 EECS 247 Lecture 25 tech Oversampled ADCs 5 2mm2 1 tech 2009 Page 8 Higher Order Modulators 1 Cascaded Modulators Summary Cascade two or more stable stages Quantization error of each stage is quantized by the succeeding stage s and subtracted digitally Order of noise shaping equals sum of the orders of the stages Quantization noise cancellation depends on the precision of analog digital signal paths Quantization noise further randomized less limit cycle oscillation problems Typically no potential instability EECS 247 Lecture 25 Oversampled ADCs 2009 Page 9 Higher Order Lowpass Modulators Forward Path Multi Order Filter E z X z H z Y z N z D z Y z H z 1 X z E z 1 H z 1 H z NTF Y z 1 D z E z 1 H z D z N z Zeros of NTF poles of H z can be positioned to minimize baseband noise spectrum Main issue Ensuring stability for 3rd and higher orders EECS 247 Lecture 25 Oversampled ADCs 2009 Page 10 Overview Building behavioral models in stages A 5th order 1 Bit modulator Noise shaping Complex loop filters Stability Voltage scaling Effect of component non idealities EECS 247 Lecture 25 Oversampled ADCs 2009 Page 11 Building Models in Stages When modeling a complex system like a 5th order modulator model development proceeds in stages Each stage builds on its predecessor Design goal detect and eliminate problems at the highest possible level of abstraction Each successive stage consumes progressively more engineering time Our model development proceeds in stages Stage 0 gets to the starting line Collect references talk to veterans Stage 1 develops a practical system built with ideal sub circuits simulation Stage 2 models key sub circuit non idealities and translates the results into real world sub circuit performance specifications Real world model development includes a critical stage 3 Adding elements to earlier stages to model significant surprises found in silicon EECS 247 Lecture 25 Oversampled ADCs 2009 Page 12 Modulator Design Procedure Establish requirements Design noise transfer function NTF Determine loop filter H Synthesize filter Evaluate performance Establish stability criteria Ref R W Adams and R Schreier Stability Theory for Modulators in Delta Sigma Data Converters S Norsworthy et al eds IEEE Press 1997 EECS 247 Lecture 25 Oversampled ADCs 2009 Page 13 Example Modulator Specification Example Audio ADC Dynamic range Signal bandwidth Nyquist frequency Modulator order Oversampling ratio Sampling frequency DR B fN L M fs fN fs 18 Bits 20 kHz 44 1 kHz 5 64 2 822 MHz The order L and oversampling ratio M are chosen based on SQNR 120dB EECS 247 Lecture 25 Oversampled ADCs 2009 Page 14 Noise Transfer Function NTF z NTF dB stop band attenuation Rstop 80dB L 5 L 5 Rstop 80 B 20000 b a cheby2 L Rstop B high 20 normalize 0 b b b 1 NTF filt b a 20 Chebychev II filter chosen zeros in stop band 40 60 80 100 EECS 247 Lecture 25 104 Frequency Hz Oversampled ADCs 106 2009 Page 15 Loop Filter Characteristics H z Note For order an integrator is used instead of the high order filter shown 1st EECS 247 Lecture 25 Loopfilter H dB 100 Y z 1 NTF E z 1 H z 1 H z 1 NTF 80 60 40 20 0 20 4 10 6 10 Frequency Hz Oversampled ADCs 2009 Page 16 Modulator Topology Simulation Model Filter X b2 b1 I1 I2 I3 I4 K1 z 1 1 1 z K2 z 1 1 1 z K3 z 1 1 1 z K4 z 1 1 1 z I 1 a1 I 2 a2 I5 I 3 K5 z 1 1 1 z I 4 a4 a3 I 5 a5 Q DAC Gain
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