EECS 247- Lecture 25 Oversampled ADCs © 2009 Page 1EE247Lecture 25Oversampled ADCs (continued)– Higher order ΣΔ modulators • Last lectureÆ Cascaded ΣΔ modulators (MASH) (continued)• Single-loop single-quantizer modulators with multi-order filtering in the forward path–Example: 5thorder Lowpass ΣΔ • Modeling• Noise shaping• Effect of various nonidealities on the ΣΔ performance• Bandpass ΣΔ modulators EECS 247- Lecture 25 Oversampled ADCs © 2009 Page 2EE247Lecture 25•Administrative–Final exam: • Date: Mon. Dec. 14th• Time: 1:30pm-4:30pm (note change of time)• Location: 299 Cory (change of location)• Closed book/course notes• No calculators/cell phones/PDAs/Computers• You can bring two 8x11 paper with your own notes• Final exam covers the entire course material unless specifiedEECS 247- Lecture 25 Oversampled ADCs © 2009 Page 3EE247Lecture 25Project:– Project reports due Dec. 4th(Dec. 2ndif you are presenting on Dec. 3rd)– Please make an appointment with the instructor for a 20 minute meeting per team for Frid. Dec. 4th(for early presenters Dec. 2nd)– Prepare to give a 5 to 10 minute presentation regarding the project during the class period on Dec. 8th(or Dec. 3rd )• Highlight the important aspects of your approach towards the implementation of the ADC• If the project is joint effort, both team members should present• Email your PowerPoint presentation files to H.K. two hours priorto class to conserve class timeEECS 247- Lecture 25 Oversampled ADCs © 2009 Page 4EE247Lecture 25• Homework for oversampled data converters– Due to the time consuming nature of the project, homework covering oversampled converters will not be given. Please review relevant previous year homeworks & solutions e.g.– http://www-inst.eecs.berkeley.edu/~ee247/fa07/files07/homework/HW9_2_07.pdf– http://www-inst.eecs.berkeley.edu/~ee247/fa07/files07/homework/HW9_sol_Lynn_Wang.pdfEECS 247- Lecture 25 Oversampled ADCs © 2009 Page 5Example: 2-1 Cascaded ΣΔ ModulatorsAccuracy of < +−3%Æ 2dB loss in DRRef: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp. 193 - 202, March 1994. EECS 247- Lecture 25 Oversampled ADCs © 2009 Page 62-1 Cascaded ΣΔ ModulatorsEffect of gain parameters on signal-to-noise ratioRef: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp. 193 - 202, March 1994.EECS 247- Lecture 25 Oversampled ADCs © 2009 Page 72-1 Cascaded ΣΔ ModulatorsMeasured Dynamic Range Versus Oversampling RatioRef: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp. 193 - 202, March 1994. 3dB/OctaveTheoretical SQNR21dB/OctaveEECS 247- Lecture 25 Oversampled ADCs © 2009 Page 8Comparison of 2ndorder & Cascaded (2-1) ΣΔ ModulatorTest Results5.2mm2 (1μ tech.)0.39mm2 (1μ tech.)Active Area47.2mW13.8mWPower Dissipation8Vppd5V supply4Vppd5V supplyDifferential input range 128 (theoretical ÆSQNR=128dB, 21bit!)256 (theoretical ÆSQNR=109dB, 18bit)Oversampling rate98dB94dBPeak SNDR104dB (17-bits)98dB (16-bits)Dynamic Range(2+1) Order2ndorderArchitectureWilliams, JSSC 3/94Brandt ,JSSC 4/91ReferenceDigital Audio Application, fN =44.1kHz(Does not include Decimator)EECS 247- Lecture 25 Oversampled ADCs © 2009 Page 9Higher Order ΣΔ Modulators(1) Cascaded Modulators Summary• Cascade two or more stable ΣΔ stages• Quantization error of each stage is quantized by the succeeding stage/s and subtracted digitally • Order of noise shaping equals sum of the orders of the stages• Quantization noise cancellation depends on the precision of analog/digital signal paths• Quantization noise further randomized Æ less limit cycle oscillation problems• Typically, no potential instabilityEECS 247- Lecture 25 Oversampled ADCs © 2009 Page 10Higher Order Lowpass ΣΔ ModulatorsForward Path Multi-Order Filter• Zeros of NTF (poles of H(z)) can be positioned to minimize baseband noise spectrum• Main issue Æ Ensuring stability for 3rdand higher orders () 1() () ()1() 1()HzYz Xz EzHz Hz=+++ΣE(z)X(z)Y(z)()()()NDzHzz=ΣY( z ) 1 D( z )NTF = E(z) 1 H(z) D(z) N(z)==++EECS 247- Lecture 25 Oversampled ADCs © 2009 Page 11Overview• Building behavioral models in stages•A 5th-order, 1-Bit ΣΔ modulator– Noise shaping – Complex loop filters– Stability– Voltage scaling– Effect of component non-idealitiesEECS 247- Lecture 25 Oversampled ADCs © 2009 Page 12Building Models in Stages• When modeling a complex system like a 5th-order ΣΔ modulator, model development proceeds in stages– Each stage builds on its predecessor• Design goal Æ detect and eliminate problems at the highest possible level of abstraction– Each successive stage consumes progressively more engineering time•Our ΣΔ model development proceeds in stages:– Stage 0 gets to the starting line: Collect references, talk to veterans– Stage 1 develops a practical system built with idealsub-circuits & simulation– Stage 2 models key sub-circuit non-idealitiesand translates the results into real-world sub-circuit performance specifications – Real-world model development includes a critical stage 3: Adding elements to earlier stages to model significant surprises found in siliconEECS 247- Lecture 25 Oversampled ADCs © 2009 Page 13ΣΔ Modulator Design• Procedure– Establish requirements– Design noise-transfer function, NTF– Determine loop-filter, H– Synthesize filter– Evaluate performance, – Establish stability criteriaRef: R. W. Adams and R. Schreier, “Stability Theory for ΔΣ Modulators,” in Delta-Sigma Data Converters- S. Norsworthy et al. (eds), IEEE Press, 1997EECS 247- Lecture 25
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