EE247 Lecture 23 ADC Converters Techniques to reduce flash ADC complexity Interpolating continued Folding Multi Step ADCs Two Step flash Pipelined ADCs EECS 247 Lecture 23 Data Converters 2006 H K Page 1 Summary Last Lecture ADC Converters Comparator design continued Comparator architecture examples Techniques to reduce flash ADC complexity Interpolating to be continued EECS 247 Lecture 23 Data Converters 2006 H K Page 2 Interpolation Idea Reduce number of preamps instead interpolate between preamp outputs Reduced number of preamps Reduced input capacitance Reduced area power dissipation Same number of latches 2B 1 Important side benefit Decreased sensitivity to preamp offset Improved DNL EECS 247 Lecture 23 Data Converters 2006 H K Page 3 Preamp Output Vin A2 0 6 A2 A1 Preamp Output 0 4 Vref2 A1 Vref1 0 2 0 Zero crossings to be detected by latches at Vin 0 2 0 4 0 6 0 0 5 1 Vref1 1 5 Vin 2 2 5 Vref2 EECS 247 Lecture 23 Data Converters 3 Vref1 1 Vref2 2 2006 H K Page 4 Preamp Output Differential Preamp Output 0 5 Differential output crossings Vin Vref1 1 Vref2 2 A2 A2 A1 A 1 0 0 5 0 0 5 1 1 5 2 A1 A2 0 5 2 5 3 A1 A2 Note Additional crossing of A1 A2 A2 A1 A1 A2 cross zero at 0 Vref12 0 5 1 2 1 5 0 5 0 0 5 1 1 5 2 2 5 3 Vin EECS 247 Lecture 23 Data Converters 2006 H K Page 5 Interpolation in Flash ADC Vin A2 A1 Compare A2 A1 Comparator output is sign of A1 A2 EECS 247 Lecture 23 Data Converters Half as many reference voltages and preamps Interpolation factor x2 Example For 10bit straight Flash ADC need 2B 1024 preamps compared 2B 1 512 for x2 interpolation Possible to accomplish higher interpolation factor Interpolation at the output of preamps 2006 H K Page 6 Interpolation in Flash ADC Preamp Output Interpolation Vin Z A2 Vo2 Interpolate between two consecutive output via impedance Z Z Vo1 5 Vo1 Vo2 2 Z A1 Vo1 Z Choices of Z 1 Resistors Kimura 2 Capacitors Kusumoto 3 Current mode Roovers Ref H Kimura et al A 10 b 300 MHz Interpolated Parallel A D Converter JSSC pp 438 446 April 1993 K Kusumoto et al A 10 b 20 MHz 30 mW pipelined interpolating CMOS ADC JSSC pp 1200 1206 December 1993 R Roovers et al A 175 Ms s 6 b 160 mW 3 3 V CMOS A D converter JSSC pp 938 944 July 1996 EECS 247 Lecture 23 Data Converters 2006 H K Page 7 Higher Order Resistive Interpolation Resistors produce additional levels With 4 resistors per side the interpolation factor M 8 M ratio of latches preamps Ref H Kimura et al A 10 b 300 MHz Interpolated Parallel A D Converter JSSC April 1993 pp 438 446 EECS 247 Lecture 23 Data Converters 2006 H K Page 8 DNL Improvement Preamp offset distributed over M resistively interpolated voltages Impact on DNL divided by M Latch offset divided by gain of preamp Use large preamp gain Next Investigate how large preamp gain can be Ref H Kimura et al A 10 b 300 MHz Interpolated Parallel A D Converter JSSC April 1993 pp 438 446 EECS 247 Lecture 23 Data Converters 2006 H K Page 9 Preamp Output Preamp Input Range Linear region of transfer curve not overlapping 0 5 A2 A2 Dead zone in the interpolated transfer curve Results in error A1 0 A1 0 5 0 0 5 1 1 5 2 A1 A2 0 5 2 5 3 Linear consecutive preamp input ranges must overlap i e range A1 A2 0 0 5 0 0 5 1 1 5 2 Vin EECS 247 Lecture 23 Data Converters 2 5 If linear region of preamp transfer curve do not overlap 3 Sets upper bound on preamp gain VDD 2006 H K Page 10 Interpolated Parallel ADC 10 bit overall resolution 7 bit flash 127 preamps and 128 resistors x8 interpolation Ref H Kimura et al A 10 b 300 MHz Interpolated Parallel A D Converter JSSC April 1993 pp 438 446 EECS 247 Lecture 23 Data Converters 2006 H K Page 11 Measured Performance 7 3 Low input capacitance Ref H Kimura et al A 10 b 300 MHz Interpolated Parallel A D Converter JSSC April 1993 pp 438 446 EECS 247 Lecture 23 Data Converters 2006 H K Page 12 Interpolation Summary Consecutive preamp transfer curve need to have overlap Limits gain of preamp to VDD The added impedance at the output of the preamp typically reduces the bandwidth and affects the maximum achievable frequencies DNL due to preamp offset reduces by interpolation factor M Interpolation reduces of preamps and thus reduces input Chowever the of required latches the same as straight Flash Use folding to reduce the of latches EECS 247 Lecture 23 Data Converters 2006 H K Page 13 Folding Converter MSB ADC VIN LSB ADC L O G I C Digital Output Folding Circuit Two ADCs operating in parallel MSB ADC Folder LSB ADC Significantly fewer comparators than flash Fast Typically nonidealities in folder limit resolution to 10Bits EECS 247 Lecture 23 Data Converters 2006 H K Page 14 Example Folding Factor of 4 Folding factor number of folds MSB Vout bits 11 Folder maps input to smaller range MSB ADC determines which fold input is in 10 LSB ADC determines position within fold 01 Logic circuit combines LSB and MSB results 00 To LSB Quantizer Vin VFS 2 VFS EECS 247 Lecture 23 Data Converters 2006 H K Page 15 Example Folding Factor of 4 Vout How are folds generated Fold 1 Fold 2 Fold 3 Fold 4 Vout Vin Vout Vin VFS 2 Vout Vin VFS 2 Vout Vin VFS Note Sign change every other fold reference shift 11 10 01 00 1 2 3 Vin VFS 2 EECS 247 Lecture 23 Data Converters 4 VFS 2006 H K Page 16 Generating Folds via Source Couple Pairs VDD R1 R2 Vo M1 M2 Vref1 M3 IS M4 Vref2 M5 M6 Vref3 M7 IS IS M8 Vref4 IS Vin Vref1 Vref2 Vref3 Vref4 As Vin changes only one of M1 M3 M5 M7 is on depending on the input level EECS 247 Lecture 23 Data Converters 2006 H K Page 17 CMOS Folder Output Folder Output 0 5 Ideal Folder 0 Error Ideal Real 0 5 CMOS Folder 0 0 5 1 1 5 2 2 5 3 3 5 4 CMOS folder transfer curve max min portions Rounded Accurate at zero crossings 0 1 0 05 0 0 05 0 1 0 0 5 1 1 5 2 2 5 3 3 5 4 In fact most folding ADCs do not use the folds but only the zero crossings Vin EECS 247 Lecture 23 Data Converters 2006 H K Page 18 Parallel Folders Using Only Zero Crossings Vin Folder 4 Comparator Vref 3 4 Folder 3 Comparator Vref 2 4 Logic LSB bits to be combined with MSB bits Folder 2 Comparator Vref 1 4 Folder 1 Comparator Vref 0 …
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