EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 1EE247Lecture 23ADC Converters–Techniques to reduce flash ADC complexity• Interpolating (continued)• Folding• Multi-Step ADCs– Two-Step flash– Pipelined ADCsEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 2Summary Last LectureADC Converters– Comparator design (continued)• Comparator architecture examples– Techniques to reduce flash ADC complexity• Interpolating (to be continued)EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 3Interpolation• Idea– Reduce number of preamps & instead interpolate between preamp outputs• Reduced number of preamps– Reduced input capacitance– Reduced area, power dissipation• Same number of latches (2B-1)• Important “side-benefit”– Decreased sensitivity to preamp offset Improved DNLEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 4Preamp OutputZero crossings (to be detected by latches) at Vin=Vref1= 1 ΔVref2= 2 Δ0 0.511.5 2 2.5 3-0.6-0.4-0.200.20.40.6Vin /ΔPreamp OutputA2A1VinA2A1Vref1Vref2Vref1Vref2EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 5Differential Preamp OutputDifferential output crossings @ Vin=Vref1= 1 ΔVref2= 2 ΔNote: Additional crossing ofA1&-A2(A2&-A1) A1+A2cross zero at:Vref12= 0.5*(1+2) Δ=1.5Δ0 0.5 1 1.5 2 2.5 3-0.500.5Preamp Output0 0.5 1 1.5 2 2.5 3A1+A2A2-A2A1-A1A1+A2Vin / Δ-0.500.5EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 6Interpolation in Flash ADCHalf as many reference voltages and preamps Interpolation factor:x2Example: For 10bit straight FlashADC need 2B=1024 preamps compared 2B-1=512 for x2 interpolationPossible to accomplish higher interpolation factor Interpolation at the output of preampsVinA1A2Compare A2& -A1 Comparator output is sign of A1+A2EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 7Interpolation in Flash ADCPreamp Output InterpolationInterpolate between two consecutive output via impedance ZChoices of Z:1. Resistors (Kimura)2. Capacitors (Kusumoto)3. Current mode (Roovers)VinA1A2ZZZVo1Vo2Vo1.5 = (Vo1+Vo2)/2Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC, pp. 438-446, April 1993K. Kusumoto et al, "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," JSSC, pp.1200 -1206, December 1993. R. Roovers et al, "A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter," JSSC, pp. 938 - 944, July 1996. Z......EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 8Higher Order Resistive InterpolationRef: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,”JSSC April 1993, pp. 438-446• Resistors produce additional levels• With 4 resistors per side, the “interpolation factor”M=8(M ratio of latches/preamps)EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 9DNL Improvement• Preamp offset distributed over M resistively interpolated voltages: Impact on DNL divided by M• Latch offset divided by gain of preamp Use “large” preamp gain Next: Investigate how large preamp gain can beRef: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,”JSSC April 1993, pp. 438-446EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 10Preamp Input RangeIf linear region of preamp transfer curve do not overlap Dead-zone in the interpolated transfer curve! Results in error Linear consecutive preamp input ranges must overlapi.e. range > ΔSets upper bound on preamp gain <VDD/ Δ0 0.5 1 1.5 2 2.5 3A2-A2A1-A10 0.5 1 1.5 2 2.5 3-0.500.5A1+A2Preamp OutputA1+A2Vin / ΔLinear region of transfer curve not overlapping-0.500.5EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 11Interpolated-Parallel ADCRef: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp. 438-446 10-bit overall resolution:7-bit flash (127 preamps and 128 resistors) & x8 interpolationEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 12Measured PerformanceRef: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp. 438-446 (7+3)Low inputcapacitanceEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 13Interpolation Summary• Consecutive preamp transfer curve need to have overlap Limits gain of preamp to ~VDD/Δ • The added impedance at the output of the preamp typically reduces the bandwidth and affects the maximum achievable frequencies• DNL due to preamp offset reduces by interpolation factor M• Interpolation reduces # of preamps and thus reduces input C-however, the # of required latches the same as “straight” Flash Use folding to reduce the # of latchesEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 14Folding Converter• Two ADCs operating in parallel– MSB ADC– Folder + LSB ADC• Significantly fewer comparators than flash •Fast• Typically, nonidealities in folder limit resolution to ~10BitsLOGICLSBADCMSBADCFolding CircuitVINDigitalOutputEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 15Example: Folding Factor of 4VinVFSVFS/2Vout00011011ToLSB Quantizer MSBbits• Folding factornumber of folds• Folder maps input to smaller range• MSB ADC determines which fold input is in• LSB ADC determines position within fold• Logic circuit combines LSB and MSB resultsEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 16Example: Folding Factor of 4VinVFSVFS/2Vout00011011• How are folds generated?• Note: Sign change every other fold + reference shiftFold 1 Vout=+ VinFold 2 Vout= - Vin + VFS/2Fold 3 Vout=+ Vin -VFS/2Fold 4 Vout= - Vin + VFS1324EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 17Generating Foldsvia Source-Couple PairsM1 M2ISVref1M3 M4ISVref2M5 M6ISVref3M7 M8ISVref4R1 R2VDD-Vo+VinVref1 < Vref2 < Vref3 < Vref4As Vin changes, only one of M1, M3, M5, M7 is on depending on the input level EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 18CMOS Folder OutputCMOS folder transfer curve max. min. portions: Rounded Accurate at zero-crossingsIn fact, most folding ADCs do not use the folds, but only the zero-crossings!0 0.5 1 1.5 2 2.5 3 3.5 4-0.500.5Folder Output0 0.5 1 1.5 2 2.5 3 3.5 4-0.1-0.0500.050.1Error (Ideal-Real)Vin/ΔIdeal FolderCMOS FolderEECS 247 Lecture 23: Data Converters © 2006 H.K. Page 19Parallel Folders Using Only Zero-CrossingsVref+ 3/4 * ΔComparatorFolder 3Folder 2Folder 1Folder 4LogicVref+ 2/4 * ΔVref+ 1/4 * ΔVref+ 0/4 * ΔVinLSB bits(to be combined with MSB
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