EE247 Lecture 16 D A converters continued Current based DACs unit element versus binary weighted R 2R type DACs Static performance Component matching systematic random errors Practical aspects of current switched DACs Segmented current switched DACs DAC self calibration techniques Current copiers Dynamic element matching ADC Converters Sampling Sampling switch induced distortion Sampling switch charge injection EECS 247 Lecture 16 Data Converters 2006 H K Page 1 Summary Last Lecture Data Converters Practical aspects of converter testing Evaluation board considerations D A converter design Architectures Voltage based Resistor string type Resistor string incorporating interpolation Charge based Serial charge redistribution DAC Parallel charge scaling DAC Current based Unit element Binary weighted EECS 247 Lecture 16 Data Converters 2006 H K Page 2 Current Source DAC Unit Element Iref Iout Iref Iref Iref Unit elements 2B 1 current sources switches Monotonicity does not depend on element matching Suited for both MOS and BJT technologies Output resistance of current source causes gain error EECS 247 Lecture 16 Data Converters 2006 H K Page 3 Current Source DAC Unit Element R Vout Iref Iref Iref Iref Output resistance of current source gain error problem Use transresistance amplifier Current source output held virtual ground Error due to current source output resistance eliminated New issues offset speed of the amplifier EECS 247 Lecture 16 Data Converters 2006 H K Page 4 Current Source DAC Binary Weighted 2B 1 Iref Iout 4 Iref 2Iref Iref Binary weighted B current sources switches 2B 1 unit current sources but less of switches Monotonicity depends on element matching EECS 247 Lecture 16 Data Converters 2006 H K Page 5 R 2R Ladder Type DAC R 2R DAC Basics R Simple R network divides both voltage current by 2 V V 2 I 2 I 2 I 2R 2R Increase of bits by replicating circuit EECS 247 Lecture 16 Data Converters 2006 H K Page 6 R 2R Ladder DAC Iout VB R R VEE 2R 2R 2R R 2R 2R 2R R Emitter follower added to convert to high output impedance current sources Series switch resistance does not impair performance EECS 247 Lecture 16 Data Converters 2006 H K Page 7 R 2R Ladder DAC How Does it Work Consider a simple 3bit R 2R DAC Iout VB VEE 4Aunit 2R R EECS 247 Lecture 16 Data Converters 2Aunit Aunit 2R 2R Aunit 2R R 2006 H K Page 8 R 2R Ladder DAC How Does it Work Simple 3bit DAC 1 Consolidate first two stages I2 I3 VB VEE IT I1 I2 I3 VB I1 IT Q3 Q2 Aunit 4Aunit 2Aunit 2Aunit 2R 2R R 2R R R Q3 Q2 Q1 QT 4Aunit 2Aunit Aunit 2R R 2R R 2R VEE EECS 247 Lecture 16 Data Converters 2006 H K Page 9 R 2R Ladder DAC How Does it Work Simple 3bit DAC2 Consolidate next two stages I2 I3 VB VEE I1 IT Q3 Q2 4Aunit 2Aunit 2R R 2R R I2 I1 IT I3 VB Q3 Q2 2Aunit 4Aunit 4Aunit R 2R R R VEE I I I I3 I2 I1 IT I3 T ot al I2 T ot a l I1 To t al 2 4 8 EECS 247 Lecture 16 Data Converters 2006 H K Page 10 R 2R Ladder DAC How Does it Work Consider a simple 3bit R 2R DAC Iout VB 4Aunit 4I VEE Aunit 2Aunit 2R 2I R 2R 4I Aunit 2R I I 2R R 2I Ref B Razavi Data Conversion System Design IEEE Press 1995 page 84 87 EECS 247 Lecture 16 Data Converters 2006 H K Page 11 R 2R Ladder DAC RTotal R Vout VB 16I VEE 2R 8I R 2R 4I R 2R 2I R 16I 8I 4I 2R I 2R I 2R R 2I Transresistance amplifier added to Convert current to voltage Generate virtual ground current summing node so that output impedance of current sources do not cause error Issue error due to opamp offset EECS 247 Lecture 16 Data Converters 2006 H K Page 12 R 2R Ladder DAC Opamp Offset Issue R out in 1 Vos Vos R Total R RTotal I f R Total l a r g e ou t in Vos Vos Vout Vos I f RTotal no t l a r g e R ou t in 1 Vos Vos RTotal Pro bl e m Offset Model S in c e RTotal is c o d e d e pe n da n t o ut Vos wo u ld b e c o de d e p e n d a n t G iv e s ris e to I NL D N L EECS 247 Lecture 16 Data Converters 2006 H K Page 13 R 2R Ladder Summary Advantages Resistor ratios only x2 Does not require precision capacitors Disadvantages Total device emitter area AEx2B Not practical for high resolution DACs INL DNL error due to amplifier offset EECS 247 Lecture 16 Data Converters 2006 H K Page 14 Static DAC Errors INL DNL Static DAC errors mainly due to component mismatch Systematic errors Contact resistance Edge effects in capacitor arrays Process gradients Finite current source output resistance Random variations Lithography etc Often Gaussian distribution central limit theorem Ref C Conroy et al Statistical Design Techniques for D A Converters JSSC Aug 1989 pp 1118 28 EECS 247 Lecture 16 Data Converters 2006 H K Page 15 Current Source DAC DNL INL Due to Element Mismatch Iref Iref Iref Iref Vout Iref Iref I Iref I Simplified example 3 bit DAC Assume only two of the current sources mismatched 4 5 EECS 247 Lecture 16 Data Converters 2006 H K Page 16 Current Source DAC DNL INL Due to Element Mismatch DN L m seg men t m V L S B V LSB DN L 4 7 Iref R seg men t 4 V L S B V LSB Analog Output 6 5 I I R IR 4 IR DN L 4 I I LSB 3 I I R IR 2 DN L 5 IR 1xIref R DN L 5 I I L S B IN Lmax I I L S B Digital Input 0 000 001 010 011 100 101 110 111 EECS 247 Lecture 16 Data Converters 2006 H K Page 17 Component Mismatch Probability Distribution Function Component parameters Random variables Each component is the product of many fabrication steps Most fabrication steps includes random variations Overall component variation product of several random variables Assuming each of these variables have a uniform distribution Joint pdf of a random variable affected by two uniformly distribution is the convolution of the two uniform pdfs pdf f x1 pdf f x2 pdf f x1 x2 pdf f x3 x4 pdf f x1 x2 EECS 247 Lecture 16 Data Converters Gaussian pdf pdf f xm xn 2006 H K Page 18 Gaussian Distribution Probability density p x 0 4 0 3 0 2 0 1 0 x 2 1 p x e 2 3 2 1 2 2 0 x 1 2 3 where standard deviation E X 2 2 EECS 247 Lecture 16 Data Converters 2006 H K Page 19 2 1 X x e 2 dx 2 …
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