EE247 Lecture 23 Pipelined ADCs continued Effect gain stage sub DAC non idealities on overall ADC performance Digital calibration continued Correction for inter stage gain nonlinearity Implementation Practical circuits Stage scaling Combining the bits Stage implementation Circuits Noise budgeting How many bits per stage Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 1 Pipeline ADC Block Diagram DAC ADC Vin Stage 1 B1 Bits Vres1 Stage 2 B2 Bits Vres2 MSB Stage k Bk Bits LSB Align and Combine Data Digital Output B1 B2 Bk Bits Idea Cascade several low resolution stages to obtain high overall resolution e g 10bit ADC can be built with series of 10 ADCs each 1 bit only Each stage performs coarse A D conversion and computes its quantization error or residue EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 2 Summary So Far Pipelined A D Converters Vref Vin B1 bits T H Gain 2B1eff Vref B2 bits Vref B2 22B2eff B3 bits Vref ADC B3 2 2B3eff Cascade of low resolution stages By adding inter stage gain 2Beff No need to scale down Vref for stages down the pipe Reduced accuracy requirement for stages coming after stage 1 Addition of Track Hold function to interstage gain stages can operate concurrently Throughput increased to as high as one sample per clock cycle Latency function of number of stages conversion per stage Correction for circuit non idealities Built in redundancy compensate for sub ADC inaccuracies such as comparator offset interstage gain G 2Bneff Bneff Bn EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 3 Pipeline ADC Error Compensation Non idealities associated with sub ADCs sub DACs and gain stages error in overall pipeline ADC performance Need to find means to tolerate correct errors Important sources of error Sub ADC errors comparator offset Gain stage offset Gain stage error Sub DAC error EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 4 Gain Stage Gain Inaccuracy Gain error can be compensated in digital domain Digital Calibration Problem Need to measure calibrate digital correction coefficient Example Calibrate 1 bit first stage Objective Measure G in digital domain EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 5 ADC Model Vref G Vin 2 Vres1 G Vin VDAC VDAC D 0 0 G Vin EECS 247 Lecture 23 VDAC D 1 Vref 2 Pipelined ADCs 2008 H K Page 6 Gain Stage Inacurracy Calibration Step 1 Vref Vin const 1 bit ADC Backend Dback 1 1 bit DAC M U X D Vres1 1 G 1 Vres1 G Vin Vref 2 1 Dback 1 G EECS 247 Lecture 23 V in Vref 2 Vref store Pipelined ADCs 2008 H K Page 7 Gain Stage Inacurracy Calibration Step 2 Vin const 1 bit ADC G Backend Dback 2 1 bit DAC M U X D Vres1 2 Vref 0 Vres1 2 Dback EECS 247 Lecture 23 G Vin 0 2 G Vin 0 store Vref Pipelined ADCs 2008 H K Page 8 Gain Stage Inacurracy Calibration Evaluate Dback Dback 1 2 G G V in Vref 2 Vref Vin 0 Vref 1 1 2 Dback Dback G 2 To minimize the effect of backend ADC noise perform measurement several times and take the average EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 9 Accuracy Bootstrapping Vin ADC Vres1 G 1 q1 Dout D1 1 Gd1 Vres2 G 2 q2 D2 Vres n 1 G n 1 q n 1 1 Gd2 G q2 G 1 2 n q2 n 1 Dout Vin ADC q1 1 1 Gd 1 Gd 1 Gd 2 Gdj j 1 qn D n 1 Dn 1 Gd n 1 G 1 n 1 qn n 1 G d n 1 Gdj j 1 Highest sensitivity to gain errors in front end stages EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 10 Accuracy Bootstrapping Direction of Calibration Vin Stage 1 Stage 2 Stage 3 Sufficiently Accurate Stage k Bn bits Ref A N Karanicolas et al A 15 b 1 Msample s digitally self calibrated pipeline ADC IEEE J Of Solid State Circuits pp 1207 15 Dec 1993 E G Soenen et al An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs TCAS II pp 143 153 March 1995 L Singer et al A 12 b 65 MSample s CMOS ADC with 82 dB SFDR at 120 MHz ISSCC 2000 Digest of Tech Papers pp 38 9 calibration in opposite direction EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 11 Pipeline ADC Errors Non idealities associated with sub ADCs sub DACs and gain stages error in overall pipeline ADC performance Need to find means to tolerate correct errors Important sources of error Sub ADC errors comparator offset Gain stage offset Gain stage error Sub DAC error EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 12 DAC Errors Vin B1 bit ADC B1 bit DAC DAC Backend D Dout Vres1 G Dback 1 G Can be corrected digitally as well Same calibration concept as gain errors Vary DAC codes measure errors via backend ADC EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 13 DAC Calibration Step 1 Vin const B1 bit ADC M U X D B1 bit DAC G Vres1 Backend DAC 0 0 Dout 1 G Dback DAC 0 equivalent to offset ignore EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 14 DAC Calibration Step 2 2B1 Vin const B1 bit ADC D M U X B1 bit DAC 1 2B1 1 Dout G Vres1 Backend DAC 1 2B1 1 Cal Register 1 G Dback Stepping through DAC codes 1 2B1 1 yields all incremental correction values Measurements repeated and averages to account for variance associated with noise EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 15 Pipeline ADC Example Calibration Hardware Above block diagram may seem extensive however in current fine line CMOS technologies digital portion of a pipeline ADCs consume insignificant power and area compared to the analog sections Ref E G Soenen et al An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs TCAS II pp 143 153 March 1995 EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 16 Pipelined ADC Error Correction Calibration Summary VOS VIN1 ADC ADC 23 VRES1 gain DAC a3V3 DAC D1 Error Correction Calibration ADC Vos Redundancy either same stage or next stage gain Digital adjustment DAC Either sufficient component matching or digital calibration Inter stage amplifier non linearity EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 17 Inter stage Gain Nonlinearity Invert gain stage non linear polynomial Express error as function of VRES1 Push error into digital domain through backend Ref B Murmann and B E Boser A 12 b 75MS s Pipelined ADC using Open Loop Residue Amplification ISSCC Dig Techn Papers pp 328 329 2003 EECS 247 Lecture 23 Pipelined ADCs 2008 H K Page 18 Inter stage Gain Nonlinearity a3VX3 VX 23 gain VRES1 Backend p2 DB a3 2 gain3 DB corr DB p2 3 DB p2 p2DB3 3p22DB5 …
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