EE247 Lecture 19 ADC Converters ADC architectures Comparator architectures High gain amplifier with differential analog input single ended large swing output Latched comparators in response to a strobe input stage disabled digital output stored in a latch till next strobe Sample data comparators Offset cancellation EECS 247 Lecture 19 Data Converters 2004 H K Page 1 ADC Architectures Slope Converters Successive approximation Flash Folding Time interleaved parallel converter Residue type ADCs Two step Pipeline Algorithmic Oversampled ADCs EECS 247 Lecture 19 Data Converters 2004 H K Page 2 Residue Type ADC Partial Digital Output VIN Error coarse ADC 1 6 Bit DAC S H Gain optional Quantization error output residuum enables cascading for higher resolution Great flexibility for stages flash oversampling ADC Optional S H enables parallelism pipelining Fast one clock per conversion with S H latency EECS 247 Lecture 19 Data Converters 2004 H K Page 3 Pipelined ADC VIN Stage 1 B1 Bits Stage 2 B2 Bits Stage K Bk Bits Digital Correction Logic Digital output up to B1 B2 Bk Bits Approaches speed of flash but much lower complexity One clock per conversion but K clocks latency Efficient digital calibration possible Versatile from 16Bits 1MS s to 14Bits 100MS s EECS 247 Lecture 19 Data Converters 2004 H K Page 4 Algorithmic ADC Digital Output start of conversion VIN Shift Register Correction Logic coarse ADC 1 6 Bit Error DAC 2B S H Essentially same as pipeline but a single stage is used for all partial conversions K clocks per conversion EECS 247 Lecture 19 Data Converters 2004 H K Page 5 Oversampled ADC fs VIN fs M Digital Decimation Filter H z Digital Output DAC Hard to comprehend easy to build Input is oversampled M times faster than output rate Reduces Anti Aliasing filter requirements and capacitor size Accuracy independent of component matching Very high resolution achievable 20 Bits EECS 247 Lecture 19 Data Converters 2004 H K Page 6 Resolution Bit 16 14 12 10 8 B 1 Flash Pipeline 1 to 2 18 Su ce ss Appcro 2 nd ximivaetio Ov Or n B ers der am 1 ple Bit d 2 0 4 Throughput Rate Comparison 2 l ria Se B 6 4 2 0 0 10 1 10 10 2 10 3 4 10 5 10 Clock Cycles per Conversion EECS 247 Lecture 19 Data Converters 2004 H K Page 7 Speed Resolution Map www v corp com EECS 247 Lecture 19 Data Converters 2004 H K Page 8 High Speed A D Converters Flash Converter Comparator design considerations Binary Encoder Interpolation Folding Pipelined ADCs EECS 247 Lecture 19 Data Converters 2004 H K Page 9 Flash Converter Very fast only 1 clock cycle per conversion V REF VIN R 2 R High complexity 2B 1 comparators R Encoder Digital Output R High input capacitance R R 2 EECS 247 Lecture 19 Data Converters 2004 H K Page 10 Voltage Comparators Vin Vout Digital Output Function compare the instantaneous value of two analog signals Important features Maximum clock rate fs settling time slew rate small signal bandwidth Resolution gain offset Overdrive recovery Input capacitance and linearity Power dissipation Common mode rejection Kickback noise Ref Prof B Wooley Course notes EE315 Stanford University EECS 247 Lecture 19 Data Converters 2004 H K Page 11 Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input single ended large swing output Output swing compatible with driving digital logic circuits Open loop amplification no frequency compensation required Precise gain not required Latched comparators in response to a strobe input stage disabled digital output stored in a latch till next strobe Two options for implementation High gain amplifier simple digital latch Low gain amplifier a high sensitivity latch Sample data comparators S H input Offset cancellation Pipelined stages EECS 247 Lecture 19 Data Converters 2004 H K Page 12 Comparators w High Gain Amplification Amplify Vin min to VDD Vin min determined by ADC resolution Example 12 bit res full scale input 2V 1LSB 0 5mV For 2 5V output Av 2 5V 0 25mV 10 0 0 0 Vos 1 L S B EECS 247 Lecture 19 Data Converters 2004 H K Page 13 Comparators w High Gain Amplification fu 10 1000MHz fu unity gain frequency f 0 3dB frequency f0 fu 1GHz 100kHz AV 10 000 0 1 1 6 sec 2 f 0 Too slow Cascade of lower gain stages to broadband response EECS 247 Lecture 19 Data Converters 2004 H K Page 14 Open Loop Cascade of Amplifiers The stages identical small signal model for the cascades For 1 stage only EECS 247 Lecture 19 Data Converters 2004 H K Page 15 Open Loop Cascade of Amplifiers For Cascade of N stages EECS 247 Lecture 19 Data Converters 2004 H K Page 16 Open Loop Cascade of Amplifiers For AT DC 10 000 Example N 3 fu 1GHz AT 0 10000 f0 N 0N 1GHz 10 000 1 3 21 3 1 24 MHz 1 7 n sec 1 6 s for 1 stage 2 f0 N 5 0 N 35n sec Cascade of 3 stage speed 236 higher compared to 1 stage constant overall gain fu EECS 247 Lecture 19 Data Converters 2004 H K Page 17 Open Loop Cascade of Amplifiers Offset Voltage Cascade of amplifiers Input referred offset increases Choice of of stages important Speed vs offset tradeoff Example For 3 stage case with gain stage 22 Increase in offset 4 5 EECS 247 Lecture 19 Data Converters 2004 H K Page 18 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior t EECS 247 Lecture 19 Data Converters 2004 H K Page 19 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior EECS 247 Lecture 19 Data Converters 2004 H K Page 20 Open Loop Cascade of Amplifiers Delay C gm Delay C gm Minimum total delay broad function of N Relationship between of stages that minimize delay Nop and gain Vout Vin approximately Nop 1 1xln Vout Vin 0 79 for gain 1000 Or gain of 10dB sqrt10 per stage results in near optimum delay Ref J T Wu et al A 100 MHz pipelined CMOS comparator IEEE Journal of Solid State Circuits vol 23 pp 1379 1385 December 1988 EECS 247 Lecture 19 Data Converters 2004 H K Page 21 Offset Cancellation Disadvantage of using cascade of amplifiers Increased overall input referred offset Sampled data cascade of amplifiers Vos can be cancelled Store on ac coupling capacitors in series with amplifier stages Offset associated with a specific amplifier can be cancelled by storing it in series with either the input or the output of that stage EECS 247 Lecture 19 Data Converters 2004 H K Page 22 Offset Cancellation Output Series Cancellation Amp modeled as ideal Vos input referred Store offset S1 S4 open S2 S3 closed VC AxVOS EECS 247 Lecture 19 Data Converters 2004 H K Page 23 Offset Cancellation Output Series
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