EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 1EE247Lecture 19ADC Converters- ADC architectures- Comparator architectures• High gain amplifier with differential analog input & single-ended large swing output• Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe• Sample-data comparators– Offset cancellationEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 2ADC Architectures• Slope Converters• Successive approximation• Flash• Folding• Time-interleaved / parallel converter• Residue type ADCs– Two-step– Pipeline– Algorithmic– …• Oversampled ADCsEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 3Residue Type ADC• Quantization error output (“residuum”) enables cascading for higher resolution• Great flexibility for stages: flash, oversampling ADC, …• Optional S/H enables parallelism (pipelining)• Fast: one clock per conversion (with S/H), latencyS/H & Gain(optional)coarse ADC(1 ... 6 Bit)Partial Digital OutputVINErrorDACEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 4Pipelined ADC• Approaches speed of flash, but much lower complexity• One clock per conversion, but K clocks latency• Efficient digital calibration possible• Versatile: from 16Bits / 1MS/s to 14Bits / 100MS/sDigital Correction LogicStage 1B1 BitsStage 2B2 BitsStage KBk BitsDigital outputup to (B1 + B2 + ... + Bk) BitsVINEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 5Algorithmic ADC• Essentially same as pipeline, but a single stage is used for all partial conversions• K clocks per conversionS/H coarse ADC (1 ... 6 Bit)Digital OutputVINErrorDACShift Register& Correction Logicstart of conversion2BEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 6Oversampled ADC• Hard to comprehend … “easy” to build• Input is oversampled (M times faster than output rate)• Reduces Anti-Aliasing filter requirements and capacitor size• Accuracy independent of component matching• Very high resolution achievable (> 20 Bits)H(z)DigitalDecimationFilterDACVINDigitalOutputfsfs/MEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 7Throughput Rate Comparison100101102103104105024681012141618Clock Cycles per ConversionResolution [Bit]Flash, Pipeline~1 to 2Successive Approximation~B2ndOrder 1-Bit Oversampled ~2(0.4B+1)Serial ~2BEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 8Speed-Resolution Map[www.v-corp.com]EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 9High-Speed A/D Converters• Flash Converter– Comparator design considerations– Binary Encoder• Interpolation• Folding• Pipelined ADCsEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 10Flash Converter• Very fast: only 1 clock cycle per conversion• High complexity: 2B-1 comparators• High input capacitanceR/2RRRR/2REncoderDigitalOutputVINVREFEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 11Voltage ComparatorsFunction: compare the instantaneous value of two analog signalsImportant features:• Maximum clock rate fs à settling time, slew rate, small signal bandwidth• Resolutionà gain, offset• Overdrive recovery• Input capacitance (and linearity!)• Power dissipation• Common-mode rejection• Kickback noise• …+Vin-+-Vout (Digital Output)Ref: Prof. B. Wooley, Course notes EE315 Stanford UniversityEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 12Voltage ComparatorArchitecturesComparator architectures• High gain amplifier with differential analog input & single-ended large swing output– Output swing compatible with driving digital logic circuits– Open-loop amplificationà no frequency compensation required– Precise gain not required• Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe– Two options for implementation :• High-gain amplifier + simple digital latch• Low-gain amplifier + a high-sensitivity latch• Sample-data comparators– S/H input– Offset cancellation– Pipelined stagesEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 13Comparators w/ High-Gain AmplificationAmplify Vin(min) to VDD Vin(min) determined by ADC resolutionExample: 12-bit res. & full-scale input 2Và 1LSB=0.5mVà For 2.5V output:vos2.5VA10,0000.25mVV1LSB==<EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 14Comparators w/ High-Gain AmplificationToo slow!à Cascade of lower gain stages to broadband responsefu=10-1000MHz 0 0 V 0 0 =unity gain frequency, 3 frequency110010,00011.6sec2uuffdBfGHzfkHzAfτµπ=−=====EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 15Open Loop Cascade of AmplifiersThe stages identical à small-signal model for the cascades:For 1-stage only:EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 16Open Loop Cascade of AmplifiersFor Cascade of N-stages:EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 17Open Loop Cascade of AmplifiersFor |AT(DC)|=10,000( ) T 1/30 1/30 0 0 :3,=1GHz, (0)100001212410,00017sec(1.6s for 1-stage)2535secuNNNNExampleNfAGHzfMHznfnτµπτ===−====Cascade of 3-stage àspeed 236 higher compared to 1-stage (constant overall gain & fu)EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 18Open Loop Cascade of AmplifiersOffset Voltage•Cascade of amplifiersàInput-referred offset increases•Choice of # of stages importantàSpeed vs offset tradeoffExample: For 3-stage case with gain/stage ~22à Increase in offset ~ 4.5%EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 19Open Loop Cascade of AmplifiersStep Response•Assuming linear behaviortEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 20Open Loop Cascade of AmplifiersStep Response•Assuming linear behaviorEECS 247 Lecture 19: Data Converters © 2004 H.K. Page 21Open Loop Cascade of AmplifiersDelay/(C/gm)•Minimum total delay broad function of N•Relationship between # of stages that minimize delay (Nop) and gain (Vout/Vin) approximately:Nop=1.1xln(Vout/Vin) +0.79for gain <1000•Or gain of 10dB (sqrt10) per stage results in near optimum delay Delay/(C/gm)Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988. EECS 247 Lecture 19: Data Converters © 2004 H.K. Page 22Offset Cancellation•Disadvantage of using cascade of amplifiers:à Increased overall input-referred offset•Sampled-data cascade of amplifiers
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