EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 1EE247Lecture 21ADC Converters (continued)– Successive approximation ADCs (continued)–Flash ADC– Flash ADC sources of error• Sparkle code• Meta-stability– Comparator designEECS 247 Lecture 21: Data Converters © 2006 H.K. Page 2Summary of Last LectureADC Converters– Sampling (continued)• Track & hold circuits• T/H combined with summing/difference function• T/H circuit incorporating gain & offset cancellation–Electro-Static Discharge (ESD) protection– ADC architectures • Serial- slope type• Successive approximationEECS 247 Lecture 21: Data Converters © 2006 H.K. Page 3Successive Approximation ADC• High accuracy achievable (16+ Bits) • Require N clock cycles for N-bit conversion (much faster than slope type)• Moderate speed proportional to B (MHz range)VDAC/VREFTime / Clock Ticks11/23/45/8VIN1/2 3/4 5/8 11/16 21/32 41/64Example: 6-bit ADC & VIN=5/8VREFADCÆ101000DACVINControlLogicClockVREFT/HTest MSBTest MSB-1EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 4Example: SAR ADCCharge Redistribution Type• T/H inherent in DAC• Operation starts by connecting all top plate to gnd and all bottom plates to Vin• To test the MSB all top plate are opened bottom plate of 32C connected to VREF& rest of bottom plates connected to ground Æ input to comparator= -Vin+VREF/2 • Comparator is strobed to determine the polarity of input signal if - MSB=1 if + MSB=0• The process continues until all bits are determinedC2C4C8C32COutStopb1b2b3b4(msb)-Comparator16Cb3CVinVREFVinControlLogicToswitchesb0EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 5Example: SAR ADCCharge Redistribution Type•To 1storder parasitic (Cp) insensitive since top plate driven from initial 0 to final 0 by the global negative feedback• Linearity is a function of accuracy of C ratios• Possible to add a C ratio calibration cycle (see ref.)C2C4C8C32COutresetb1b2b3b4(msb)CP-Comparator16Cb3CVinVREFVinControlLogicToswitchesRef: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 19, pp. 813 - 819, December 1984. b0EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 6Flash ADC• B-bit flash ADC:–DAC generates all possible 2B-1 levels–2B-1 comparators compare VINto DAC outputs–Comparator output:• If VDAC < VIN Æ0• If VDAC> VIN Æ1–Comparator outputs form thermometer code–Encoder converts thermometer to binary codeDigitalOutputDAC2B-1ÆBEncoderVREFVINfsEECS 247 Lecture 21: Data Converters © 2006 H.K. Page 7Flash ADC ConverterExample: 3-bit ConversionEncoderfsThermometer codeB-bitsTimeVREF0011111101VINVINVREFEECS 247 Lecture 21: Data Converters © 2006 H.K. Page 8Flash Converter• Very fast: only 1 clock cycle per conversion– Half cycleÆ VIN& VDACcomparison– Half cycleÆ 2B -1 to B encoding• High complexity: 2B-1 comparators• Input capacitance of 2B-1 comparators connected to the input node:Æ High capacitance @ input nodeEncoderfsVINVREFThermometer codeB-bitsEECS 247 Lecture 21: Data Converters © 2006 H.K. Page 9Flash Converter Sources of Error• Comparator input:–Offset– Nonlinear input capacitance– Kickback noise (disturbs reference)– Signal dependent sampling time• Comparator output:– Sparkle codes (… 111101000 …)– MetastabilityR/2RRRR/2REncoderDigitalOutputVINVREFfs.....EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 10Flash ConverterExample: 8-bits ADC•8-bitsÆ 255 comparators•VREF=1V Æ 1LSB=4mV• DNL<1/2LSB ÆComparator input referred offset < 2mV•2mV =6σoffsetÆ σoffset< 0.33mVR/2RRRR/2REncoderDigitalOutputVINVREFfs.....EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 11Flash ADC ConverterExample: 8-bits ADC (continued)Æ1σOffset< 0.33mV• Let us assume in the technology used:– Voffset-per-unit-sqrt(WxL)=3 [mVxμ]– Issues:• Si area quite large• Large input capacitance• Since depending on input voltage different number of comparator input transistors would be on/off- total input capacitance varies as input variesÆ Nonlinear input capacitance could give rise to signal distortion particularly at high frequencies2023[ ]0.33 832Assuming: 9 / 4963Total input capacitance: 255 0.496 126.5 !ffsetox GS oxmVVmVWLWLCfF C CWL fFpFμμμ== →×=×=→=×=→×=Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433 - 1439, October 1989. EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 12Flash ADC ConverterExample (continued)Trade-offs:– Allowing larger DNL e.g. 1LSB instead of 0.5LSB:• Increases the maximum allowable input-referred offset voltage by a factor of 2• Decreases the required device WxL by a factor of 4• Reduces the input device area by a factor of 4• Reduces the input capacitance by a factor of 4!– Reducing the ADC resolution by 1-bit• Increases the maximum allowable input-referred offset voltage by a factor of 2• Decreases the required device WxL by a factor of 4• Reduces the input device area by a factor of 4• Reduce the input capacitance by a factor of 4– Add offset cancellation to the comparator and thus decrease the input device area– could reduce the conversion rateEECS 247 Lecture 21: Data Converters © 2006 H.K. Page 13Flash ConverterMaximum Tolerable Comparator Offset versus ADC Resolution10-111010246810VREF=1VVREF=2VAssumption: DNL=0.5LSBNote:Graph shows offset, note that depending on min acceptable yield, the derived offset numbers are associated with 2σto 6σoffset voltageADC ResolutionMaximum Comparator Voffset[mV]EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 14Typical Flash Output Encoder001110100Binary Output (negative)Thermometer to Binary encoder ROMVDD• Thermometer code Æ 1-of-n decoding• Final encoding Æ NOR ROM• Ideally, for each code, only one ROM row is activated b3b2b1b0b3 b2 b1 b0OutputÆ 0 0 1 1EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 15Sparkle CodesCorrect Output:0111Problem: Two rows are onErroneous Output:1111Æ 1/2FS error!010111010Erroneous 0 (comparator offset?)VDDb3b2b1b0EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 16Sparkle Tolerant EncoderProtects against a single sparkle.Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February 1990, pp. 997-10020010101000EECS 247
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