EE247 Lecture 21 ADC Converters continued Successive approximation ADCs continued Flash ADC Flash ADC sources of error Sparkle code Meta stability Comparator design EECS 247 Lecture 21 Data Converters 2006 H K Page 1 Summary of Last Lecture ADC Converters Sampling continued Track hold circuits T H combined with summing difference function T H circuit incorporating gain offset cancellation Electro Static Discharge ESD protection ADC architectures Serial slope type Successive approximation EECS 247 Lecture 21 Data Converters 2006 H K Page 2 Successive Approximation ADC Example 6 bit ADC VIN 5 8VREF VIN VDAC VREF T H VREF 1 DAC 1 2 3 4 5 8 1 2 Control Logic ADC 101000 3 4 5 8 11 16 21 32 41 64 VIN Clock Test Test MSB MSB 1 Time Clock Ticks High accuracy achievable 16 Bits Require N clock cycles for N bit conversion much faster than slope type Moderate speed proportional to B MHz range EECS 247 Lecture 21 Data Converters 2006 H K Page 3 Example SAR ADC Charge Redistribution Type Comparator Stop 32C b4 msb 16C 8C 4C 2C C b3 b3 b2 b1 b0 Vin To switches VREF Out C Control Logic Vin T H inherent in DAC Operation starts by connecting all top plate to gnd and all bottom plates to Vin To test the MSB all top plate are opened bottom plate of 32C connected to VREF rest of bottom plates connected to ground input to comparator Vin VREF 2 Comparator is strobed to determine the polarity of input signal if MSB 1 if MSB 0 The process continues until all bits are determined EECS 247 Lecture 21 Data Converters 2006 H K Page 4 Example SAR ADC Charge Redistribution Type reset Comparator CP 32C b4 msb 16C 8C 4C 2C b3 b3 b2 b1 b0 Vin To switches VREF Out C C Control Logic Vin 1st To order parasitic Cp insensitive since top plate driven from initial 0 to final 0 by the global negative feedback Linearity is a function of accuracy of C ratios Possible to add a C ratio calibration cycle see ref Ref H Lee D A Hodges and P R Gray A self calibrating 15 bit CMOS A D converter IEEE Journal of Solid State Circuits vol 19 pp 813 819 December 1984 EECS 247 Lecture 21 Data Converters 2006 H K Page 5 Flash ADC B bit flash ADC DAC generates all possible 2B 1 levels VREF VIN fs 2B 1 comparators compare VIN to DAC outputs Comparator output If VDAC VIN 0 If VDAC VIN 1 D A C 2B 1 B Encoder Digital Output Comparator outputs form thermometer code Encoder converts thermometer to binary code EECS 247 Lecture 21 Data Converters 2006 H K Page 6 VIN Flash ADC Converter Example 3 bit Conversion VIN VREF VREF Ther mom et code er fs 0 B bits 1 1 1 Encoder 0 1 0 1 1 1 Time EECS 247 Lecture 21 Data Converters 2006 H K Page 7 Flash Converter VIN VREF fs Half cycle VIN VDAC comparison Half cycle 2B 1 to B encoding High complexity 2B 1 comparators Encoder Very fast only 1 clock cycle per conversion Input capacitance of 2B 1 comparators connected to the input node High capacitance input node EECS 247 Lecture 21 Data Converters B bits Thermometer code 2006 H K Page 8 Flash Converter Sources of Error VREF VIN fs R 2 Comparator input R Offset Nonlinear input capacitance Kickback noise disturbs reference Signal dependent sampling time Encoder R Digital Output R R Comparator output R 2 Sparkle codes 111101000 Metastability EECS 247 Lecture 21 Data Converters 2006 H K Page 9 Flash Converter Example 8 bits ADC VREF 8 bits 255 comparators VREF 1V 1LSB 4mV VIN fs R 2 R DNL 1 2LSB Comparator input referred offset 2mV Encoder R Digital Output R R 2mV 6 offset R 2 offset 0 33mV EECS 247 Lecture 21 Data Converters 2006 H K Page 10 Flash ADC Converter Example 8 bits ADC continued 1 Offset 0 33mV Let us assume in the technology used Voffset per unit sqrt WxL 3 mVx V0 ffset 3 mV 0 33mV W L W L 83 2 2 CGS CoxW L 496 fF 3 Total input capacitance 255 0 496 126 5 pF Assuming Cox 9 fF 2 Issues Si area quite large Large input capacitance Since depending on input voltage different number of comparator input transistors would be on off total input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion particularly at high frequencies Ref M J M Pelgrom A C J Duinmaijer and A P G Welbers Matching properties of MOS transistors IEEE Journal of Solid State Circuits vol 24 pp 1433 1439 October 1989 EECS 247 Lecture 21 Data Converters 2006 H K Page 11 Flash ADC Converter Example continued Trade offs Allowing larger DNL e g 1LSB instead of 0 5LSB Increases the maximum allowable input referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduces the input capacitance by a factor of 4 Reducing the ADC resolution by 1 bit Increases the maximum allowable input referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduce the input capacitance by a factor of 4 Add offset cancellation to the comparator and thus decrease the input device area could reduce the conversion rate EECS 247 Lecture 21 Data Converters 2006 H K Page 12 Flash Converter Assumption DNL 0 5LSB Maximum Comparator Voffset mV Maximum Tolerable Comparator Offset versus ADC Resolution 102 Note Graph shows offset note that depending on min acceptable yield the derived offset numbers are associated with 2 to 6 offset voltage VREF 2V 10 VREF 1V 1 10 1 4 6 10 8 ADC Resolution EECS 247 Lecture 21 Data Converters 2006 H K Page 13 Typical Flash Output Encoder Binary Output negative VDD b3 b2 b1 b0 0 0 Thermometer code 1 of n decoding 1 Final encoding NOR ROM 0 1 Ideally for each code only one ROM row is activated 0 1 0 1 Thermometer to Binary encoder ROM EECS 247 Lecture 21 Data Converters b3 b2 b1 b0 Output 0 0 1 1 2006 H K Page 14 Sparkle Codes VDD Erroneous 0 comparator offset b3 b2 b1 b0 0 Correct Output 0111 1 1 Problem Two rows are on 0 0 1 Erroneous Output 1111 1 2FS error 1 0 1 EECS 247 Lecture 21 Data Converters 2006 H K Page 15 Sparkle Tolerant Encoder 0 0 0 1 1 0 0 0 1 0 Protects against a single sparkle Ref C Mangelsdorf et al A 400 MHz Flash Converter with Error Correction JSSC February 1990 pp 997 1002 EECS 247 Lecture 21 Data Converters 2006 H K Page 16 Meta Stability Different gates interpret metastable output X differently 0 0 Correct output 0111 Erroneous output 1111 0 1 X Solutions Extra latches following comparator high …
View Full Document
Unlocking...