EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 1EE247Lecture 12• Data Converters – Data converter testing (continued)• Measuring DNL & INL– Servo-loop– Code density testing (histogram testing)• Dynamic tests– Spectral testing Reveals ADC errors associated with dynamic behavior i.e. ADC performance as a function of frequency• Direct Discrete Fourier Transform (DFT) based measurements utilizing sinusoidal signals• DFT measurements including windowing• Relationship between: DNL & SNR, INL & SFDR• Effective number of bits (ENOB)EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 2SummaryADC Differential Nonlinearity & Integral Nonlinearity End-Point -1 0 1 2 3 4 5 6 7 80167Digital Output CodeADC Input Voltage [D]-1 LSB INL23451. Endpoints connected2. Ideal characteristics derived eliminating offset & full-scale error (same as for DNL)3. DNL deviation of code width from D(1LSB)4. INL deviation of code transition from ideal+0.5 LSB DNL error-0.5 LSB DNL errorEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 3How to measure DNL/INL?• DAC:– Simply apply digital codes and use a good voltmeter to measure corresponding analog output• ADC– Not as simple as DAC need to find "decision levels", i.e. input voltages at all code boundaries• One way: Adjust voltage source to find exact code trip points "code boundary servo"• More versatile: Histogram testingApply a signal with known amplitude distribution and analyze digital code distribution at ADC outputEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 4Code Boundary ServoC1ADCInputR2C2ADCUnder TestVREFi1i2DigitalComp.A<BBABAInputDigitalCodeADCOutputfSEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 5Code Boundary ServoADC Digital OutputADC Analog Input111110101 100011010001000D 2D 3D 4D 5D 6D 7D• i1 and i2 are small, and C1 is large (DV=it/C1), so the ADC analog input moves a small fraction of an LSB (e.g. 0.1LSB) each sampling period• For a code input of 101, the ADC analog input settles to the code boundary shownEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 6Code Boundary ServoGood DVMC1R2C2ADCVREFi1i2DigitalComp.A<BBABAInputDigitalCodeADCOutputfSEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 7Code Boundary Servo• A very good digital voltmeter (DVM) measures the analog input voltage corresponding to the desired code boundary• DVMs have some interesting properties– They can have very high resolutions (8½ decimal digit meters are inexpensive)– To achieve stable readings, DVMs average voltage measurements over multiple 60Hz ac line cycles to filter out pickup in the measurement loopEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 8Code Boundary Servo• ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs• A magnified view of an analog input glitch follows …Good DVMR2C2ADCVREFfSEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 9Code Boundary Servo• Just before the input is sampled and conversion starts, the analog input is pretty quiet• As the converter begins to quantize the signal, it kicks back chargetime01/fSanalog inputstart of conversionEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 10Code Boundary Servo• The difference between what the ADC measures and what the DVM measures is not ADC INL, it’s error in the INL measurement• How do we control this error?time01/fSanalog inputADC converts this voltageDVM measures the averageinput including the glitchEECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 11Code Boundary Servo• A large C2 reduces the effect of kick-back• At the expense of longer measurement timeGood DVMR2C2ADCVREFfSEECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 12Histogram Testing• Code boundary measurements are slow – Long testing time• Histogram testing– Apply input with known pdf (e.g. ramp or sinusoid) & quantize– Measure output pdf– Derive INL and DNL from deviation of measured pdf from expected resultEECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 13Histogram Test SetupRamp0VREFADC PCVREF• Slow (wrt conversion time) linear ramp applied to ADC• DNL derived directly from total number of occurrences of each code @ the output of the ADCTimefSEECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 14A/D Histogram Test Using Ramp SignalDigital OutputAnalog inputRampTimen.TsADCInput/OutputExample:ADC sampling rate:fs =100kHz Ts=10msec1LSB =10mVFor 0.01LSB measurement resolution:n =100 samples/code Ramp duration per code:=100x10msec=1msec Ramp slope: 10mV/msecEECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 15A/D Histogram Test Using Ramp SignalDigital OutputAnalog inputRampTimen/fsIdeal ADCInput/OutputExample:Ramp slope: 10mV/msec1LSB =10mVEach ADC code1msecfs =100kHz Ts=10msecn =100 samples/code# ofSamplesPer codeDigitalOutputnEECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 16Ramp HistogramExample: Ideal 3-Bit ADC0 1 2 3 4 5 6 7 801234567ADC characteristicsideal converter0 1 2 3 4 5 6 7020406080100120140160180200ADC output codeCode CountDigital Output CodeADC Input Voltage [D]EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 17Ramp HistogramExample: Real 3-Bit ADC Including Non-Idealities0 1 2 3 4 5 6 7 801234567ADC characteristicsideal converter+0.4 LSB DNL-0.4 LSB DNL+0.4 LSB INL0 1 2 3 4 5 6 7020406080100120140160180200ADC output codeCode CountDigital Output CodeADC Input Voltage [D]EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 18Example: 3 Bit ADCDNL Extracted from Histogram1- Remove “Over-range bins” (0
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