EE247 Lecture 12 Data Converters Data converter testing continued Measuring DNL INL Servo loop Code density testing histogram testing Dynamic tests Spectral testing Reveals ADC errors associated with dynamic behavior i e ADC performance as a function of frequency Direct Discrete Fourier Transform DFT based measurements utilizing sinusoidal signals DFT measurements including windowing Relationship between DNL SNR INL SFDR Effective number of bits ENOB EECS 247 Lecture 12 Data Converters Testing 2010 H K Page 1 Summary ADC Differential Nonlinearity Integral Nonlinearity End Point 1 Endpoints connected 0 5 LSB DNL error 2 Ideal characteristics derived eliminating offset full scale error same as for DNL 3 DNL deviation of code width from D 1LSB Digital Output Code 7 6 5 1 LSB INL 4 3 2 1 4 INL deviation of code transition from ideal 0 0 5 LSB DNL error 1 EECS 247 Lecture 11 0 1 2 3 4 5 6 ADC Input Voltage D Intro to Data Converters Performance Metrics 7 8 2010 H K Page 2 How to measure DNL INL DAC Simply apply digital codes and use a good voltmeter to measure corresponding analog output ADC Not as simple as DAC need to find decision levels i e input voltages at all code boundaries One way Adjust voltage source to find exact code trip points code boundary servo More versatile Histogram testing Apply a signal with known amplitude distribution and analyze digital code distribution at ADC output EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 2010 H K Page 3 Code Boundary Servo Input Digital Code i1 A C1 VREF fS A B Digital Comp ADC Input R2 A B B ADC Under Test C2 i2 ADC Output EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 2010 H K Page 4 Code Boundary Servo ADC Digital Output i1 and i2 are small and C1 is large DV it C1 so the ADC analog input moves a small fraction of an LSB e g 0 1LSB each sampling period For a code input of 101 the ADC analog input settles to the code boundary shown 111 110 101 100 011 010 001 000 D 2D 3D 4D 5D 6D 7D ADC Analog Input EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 2010 H K Page 5 Code Boundary Servo Input Digital Code Good DVM i1 A C1 VREF fS A B Digital Comp R2 ADC A B B C2 i2 ADC Output EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 2010 H K Page 6 Code Boundary Servo A very good digital voltmeter DVM measures the analog input voltage corresponding to the desired code boundary DVMs have some interesting properties They can have very high resolutions 8 decimal digit meters are inexpensive To achieve stable readings DVMs average voltage measurements over multiple 60Hz ac line cycles to filter out pickup in the measurement loop EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 2010 H K Page 7 Code Boundary Servo ADCs of all kinds are notorious for kicking back high frequency signal dependent glitches to their analog inputs A magnified view of an analog input glitch follows EECS 247 Lecture 11 Good DVM VREF fS R2 ADC C2 Intro to Data Converters Performance Metrics 2010 H K Page 8 Code Boundary Servo analog input Just before the input is sampled and conversion starts the analog input is pretty quiet As the converter begins to quantize the signal it kicks back charge start of conversion 0 1 fS time EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 2010 H K Page 9 Code Boundary Servo How do we control this error DVM measures the average input including the glitch analog input The difference between what the ADC measures and what the DVM measures is not ADC INL it s error in the INL measurement ADC converts this voltage 0 time EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 1 fS 2010 H K Page 10 Code Boundary Servo A large C2 reduces the effect of kick back At the expense of longer measurement time Good DVM VREF fS R2 ADC C2 EECS 247 Lecture 11 Intro to Data Converters Performance Metrics 2010 H K Page 11 Histogram Testing Code boundary measurements are slow Long testing time Histogram testing Apply input with known pdf e g ramp or sinusoid quantize Measure output pdf Derive INL and DNL from deviation of measured pdf from expected result EECS 247 Lecture 12 Data Converters Testing 2010 H K Page 12 Histogram Test Setup VREF fS Ramp VREF ADC 0 PC Time Slow wrt conversion time linear ramp applied to ADC DNL derived directly from total number of occurrences of each code the output of the ADC EECS 247 Lecture 12 Data Converters Testing 2010 H K Page 13 A D Histogram Test Using Ramp Signal Digital Output Example ADC Input Output ADC sampling rate fs 100kHz Ts 10msec 1LSB 10mV For 0 01LSB measurement resolution n 100 samples code Analog input Ramp duration per code 100x10msec 1msec n Ts Ramp Ramp slope 10mV msec Time EECS 247 Lecture 12 Data Converters Testing 2010 H K Page 14 Digital Output A D Histogram Test Using Ramp Signal Example Ramp slope 10mV msec 1LSB 10mV Each ADC code 1msec Ideal ADC Input Output Analog input fs 100kHz Ts 10msec n fs Ramp of Samples Per code Time n 100 samples code EECS 247 Lecture 12 n Digital Output Data Converters Testing 2010 H K Page 15 Ramp Histogram Example Ideal 3 Bit ADC 7 200 ADC characteristics ideal converter 180 160 Code Count Digital Output Code 6 5 4 3 140 120 100 80 2 60 1 40 0 20 0 1 2 3 4 5 6 ADC Input Voltage D EECS 247 Lecture 12 7 8 0 Data Converters Testing 0 1 2 3 4 5 6 7 ADC output code 2010 H K Page 16 Ramp Histogram Example Real 3 Bit ADC Including Non Idealities 200 ADC characteristics ideal converter 7 180 160 0 4 LSB DNL 140 Code Count Digital Output Code 6 5 120 4 100 3 0 4 LSB INL 2 80 60 1 40 0 4 LSB DNL 20 0 0 1 2 3 4 5 6 ADC Input Voltage D EECS 247 Lecture 12 7 0 8 0 1 2 3 4 5 6 7 ADC output code Data Converters Testing 2010 H K Page 17 Example 3 Bit ADC 1 Remove Over range bins 0 and full scale 2 Compute average count bin 600 6 100 in this case Code Count End bins removed DNL Extracted from Histogram 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 ADC output code EECS 247 Lecture 12 Data Converters Testing 2010 H K Page 18 Example 3 Bit ADC Process of Extracting from Histogram 3 Normalize Divide histogram by average count bin ideal bins have exactly the average count which after normalization would be 1 Non ideal bins would have a normalized value greater or smaller than 1 Normalized Code Count 1 4 1 2 1 0 …
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