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Berkeley ELENG 247A - Lecture 15

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EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 1EE247Lecture 15• D/A converters– Practical aspects of current-switched DACs (continued)– Segmented current-switched DACs– DAC dynamic non-idealities– DAC design considerations– Self calibration techniques• Current copiers• Dynamic element matching– DAC reconstruction filter• A/D converter introductionEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 2Summary Last LectureD/A converter architectures:– Resistor string DAC– Serial charge redistribution DAC– Parallel charge scaling DAC– Combination of resistor string (MSB) & binary weighted charge scaling (LSB)– Current source DAC• Unit element• Binary weighted• Static performance– Component matching-systematic & random errors• Component random variations  Gaussian pdf • INL for both unit-element & binary weight DAC: sINL= sex2B/2-1• DNL for unit-element: sDNL=se• DNL for binary-weighted sDNL=sex2B/2EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 3INL & DNL for Binary Weighted DAC• INL same as for unit element DAC• DNL depends on transition–Example:0 to 1 sDNL2= s(dI/I)21 to 2 sDNL2= 3s(dI/I)2• Consider MSB transition: 0111 …  1000 …4 IrefIrefIout2Iref2B-1Iref……………EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 4DAC DNLExample: 4bit DAC0000 0001 0010 0011 0100 0101 0110 0111 1000DigitalInputAnalog Output [Iref]8765432104IrefIref –e1Iout8IrefI8I4I2I1I2on,I1onI2on,I1offI1on• DNL depends on transition– Example:0 to 1 sDNL2= s(dIref/Iref)21 to 2 sDNL2= 3s(dIref/Iref)2..........2Iref +2e2DNL= -e1DNL=e1+2e2DNL= -e1EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 5Binary Weighted DAC DNL))DNLmaxBINL DNLmaxmax2 B 1 2 B 1 2DNLB2B/ 2112 1 222 1 20111... 1000...22eeeees s sssss s s    +• Worst-case transition occurs at mid-scale:• Example:B = 12,se= 1%sDNL= 0.64 LSBsINL= 0.32 LSB2 4 6810 12 14051015DAC Output [LSB]sDNL2/ se2DNL for a 4-Bit DACEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 6Unit Element versus Binary Weighted DACExample: B=10B2DNL1BINL21S 2 1 2460eeesss s sSignificant difference in performance and complexity!B2B2DNL1INL2 32 16S B 102eeeessssssUnit Element DACBinary Weighted DACNumber of switched elements:Requires B to (2B-1) decoder to address switches B-bit digital input can be used directlyEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 710Bit DAC DNL/INL ComparisonPlots: RMS for 100 Simulation RunsRef: C. Lin and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948 - 1958, December 1998.Note: se=2%EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 8DAC INL/DNL Summary• DAC choice of architecture has significant impact on DNL• INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision• Results assume uncorrelated random element variations• Systematic errors and correlations are usually also important and may affect final DAC performanceRef: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 9Segmented DACCombination of Unit-Element & Binary-Weighted• Objective:Compromise between unit-element and binary-weighted DAC• Approach:B1MSB bits  unit elementsB2LSB bits  binary weighted• INL: unaffected same as either architecture• DNL: Worst case occurs when LSB DAC turns off and one more MSB DAC element turns on  Same as binary weighted DAC with (B2+1) # of bits• Number of switched elements: (2B1-1) + B2Unit Element Binary WeightedVAnalogMSB (B1 bits)(B2 bits) LSB… …BTotal= B1+B2EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 10ComparisonExample:B = 12, B1= 5, B2= 7B1= 6, B2= 6Assuming: se= 1% )B122B2DNL INLINLB121222S 2 1 Bees s sss+  +DAC Architecture(B1+B2)sINL[LSB]sDNL[LSB]# of switched elementsUnit element (12+0)Segmented (6+6)Segmented (5+7)Binary weighted(0+12)0.320.320.320.320.010.1130.160.64409563+6=6931+7=3812MSB LSBEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 11Practical AspectsCurrent-Switched DACsBinary Thermometer000 0000000001 0000001010 0000011011 0000111100 0001111101 0011111110 0111111111 1111111• Unit element DACs ensure monotonicity by turning on equal-weighted current sources in succession• Typically current switching performed by differential pairs• For each diff pair, only one of the devices are on switch device mismatch not an issue• Issue: While binary weighted DAC can use the incoming binary digital word directly, unit element requires a decoder B to (2B-1) decoderEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 12Segmented Current-Switched DACExample: 8bit4MSB+4LSB• 4-bit MSB Unit element DAC + 4-bit binary weighted DAC• Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder• Digital code for both DACs stored in a registerEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 13Segmented Current-Switched DACCont’d• 4-bit MSB Unit element DAC + 4-bit binary weighted DAC• Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder• Digital code for both DACs stored in a register EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 14Segmented Current-Switched DACCont’d• MSB DecoderDomino logicExample: D4,5,6,7=1 OUT=1• Register Latched NAND gate: CTRL=1 OUT=INBRegisterDomino LogicINEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 15Segmented Current-Switched DACReference Current Considerations• Irefis referenced to


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Berkeley ELENG 247A - Lecture 15

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