EE247 Lecture 15 D A converters Practical aspects of current switched DACs continued Segmented current switched DACs DAC dynamic non idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching DAC reconstruction filter A D converter introduction EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 1 Summary Last Lecture D A converter architectures Resistor string DAC Serial charge redistribution DAC Parallel charge scaling DAC Combination of resistor string MSB binary weighted charge scaling LSB Current source DAC Unit element Binary weighted Static performance Component matching systematic random errors Component random variations Gaussian pdf INL for both unit element binary weight DAC sINL DNL for unit element sDNL se se x2B 2 1 DNL for binary weighted sDNL se x2B 2 EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 2 INL DNL for Binary Weighted DAC Iout INL same as for unit element DAC DNL depends on transition Example 2B 1 Iref 0 to 1 sDNL2 s dI I 2 1 to 2 sDNL2 3s dI I 2 4 Iref 2Iref Iref Consider MSB transition 0111 1000 EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 3 DAC DNL Example 4bit DAC Analog Output Iref Iout 8 7 I8 8Iref I2 I4 6 I1 4Iref Iref e1 4 2Iref 2e2 DNL depends on transition Example 0 to 1 sDNL2 5 s dIref Iref 2 1 to 2 sDNL2 3s dIref Iref 2 3 2 1 0 I2on I1on I2on I1off I1on DNL e1 DNL e1 2e2 DNL e1 Digital Input 0000 0001 0010 0011 0100 0101 0110 0111 1000 EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 4 Binary Weighted DAC DNL Worst case transition occurs at mid scale DNL for a 4 Bit DAC 15 sDNL2 se2 2 s DNL 2B 1 1 se2 2B 1 se2 0111 10 1000 2Bse2 s DNLmax 2B 2se 5 s INLmax 1 2 2B 1 s e 1 2 s DNLmax Example 0 2 4 8 6 10 12 14 DAC Output LSB EECS 247 Lecture 15 B 12 se 1 sDNL 0 64 LSB sINL 0 32 LSB Data Converters DAC Design Intro to ADCs 2010 Page 5 Unit Element versus Binary Weighted DAC Example B 10 Unit Element DAC s DNL 2 s e 3 2s e s DNL s e s INL 2 B 2 Binary Weighted DAC B 1 s e 1 6s e s INL 2 B 2 2 1 s e 16s e Number of switched elements S 2B 1 0 24 Requires B to 2B 1 decoder to address switches S B 10 B bit digital input can be used directly Significant difference in performance and complexity EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 6 10Bit DAC DNL INL Comparison Plots RMS for 100 Simulation Runs Ref C Lin and K Bult A 10 b 500MSample s CMOS DAC in 0 6 mm2 IEEE Journal of Solid State Circuits vol 33 pp 1948 1958 December 1998 Note se 2 EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 7 DAC INL DNL Summary DAC choice of architecture has significant impact on DNL INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision Results assume uncorrelated random element variations Systematic errors and correlations are usually also important and may affect final DAC performance Ref Kuboki S Kato K Miyakawa N Matsubara K Nonlinearity analysis of resistor string A D converters IEEE Transactions on Circuits and Systems vol CAS 29 no 6 June 1982 p 383 9 EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 8 Segmented DAC Combination of Unit Element Binary Weighted Objective Compromise between unit element and binary weighted DAC MSB B1 bits B2 bits LSB Unit Element Binary Weighted Approach B1 MSB bits unit elements B2 LSB bits binary weighted VAnalog BTotal B1 B2 INL unaffected same as either architecture DNL Worst case occurs when LSB DAC turns off and one more MSB DAC element turns on Same as binary weighted DAC with B2 1 of bits Number of switched elements 2B1 1 B2 EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 9 Comparison Example B 12 B1 5 B1 6 B2 1 s DNL 2 B2 7 B2 6 MSB s INL 2 LSB Unit element 12 0 Segmented 6 6 Segmented 5 7 Binary weighted 0 12 EECS 247 Lecture 15 s e 2s INL 2 1 se S 2B1 1 B2 Assuming se 1 DAC Architecture B1 B2 B 2 sINL LSB 0 32 0 32 0 32 0 32 sDNL LSB of switched elements 0 01 0 113 0 16 0 64 4095 63 6 69 31 7 38 12 Data Converters DAC Design Intro to ADCs 2010 Page 10 Practical Aspects Current Switched DACs Unit element DACs ensure monotonicity by turning on equal weighted current sources in succession Typically current switching performed by differential pairs For each diff pair only one of the devices are on switch device mismatch not an issue Issue While binary weighted DAC can use the incoming binary digital word directly unit element requires a decoder B to 2B 1 decoder EECS 247 Lecture 15 Binary 000 001 010 011 100 101 110 111 Thermometer 0000000 0000001 0000011 0000111 0001111 0011111 0111111 1111111 Data Converters DAC Design Intro to ADCs 2010 Page 11 Segmented Current Switched DAC Example 8bit 4MSB 4LSB 4 bit MSB Unit element DAC 4 bit binary weighted DAC Note 4 bit MSB DAC requires extra 4 to 16 bit decoder Digital code for both DACs stored in a register EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 12 Segmented Current Switched DAC Cont d 4 bit MSB Unit element DAC 4bit binary weighted DAC Note 4 bit MSB DAC requires extra 4 to 16 bit decoder Digital code for both DACs stored in a register EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 13 Segmented Current Switched DAC Cont d Domino Logic MSB Decoder Domino logic Example D4 5 6 7 1 OUT 1 IN Register Latched NAND gate CTRL 1 OUT INB EECS 247 Lecture 15 Register Data Converters DAC Design Intro to ADCs 2010 Page 14 Segmented Current Switched DAC Reference Current Considerations Iref is referenced to VDD Problem Reference current varies with supply voltage Iref VDD Vref R EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 15 Segmented Current Switched DAC Reference Current Considerations Iref is referenced to Vss GND Iref Vref Vss R 0 EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 16 DAC Dynamic Non Idealities Finite settling time Linear settling issues e g RC time constants Slew limited settling Spurious signal coupling Coupling of clock control signals to the output via switches switch charge injection Timing error related glitches Control signal timing skew EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 17 Dynamic DAC …
View Full Document
Unlocking...