EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 1Midterm Exam Statistics012345610 15 16 17 17.5 18GradeMax.=20 Number of OccurrenceMean=16Standard Deviation: 2EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 2EE247Lecture 18• ADC Converters– Sampling (continued)• Sampling switch considerations– Switch induced distortion• Sampling switch conductance dependence on input voltage• Clock voltage boosters– Sampling switch charge injection & clock feedthrough• Complementary switch• Use of dummy device• Bottom-plate switching– Track & hold circuits– T/H circuit incorporating gain & offset cancellationEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 3Summary of Last Lecture• DAC Converters (continued)• Dynamic element matching– DAC reconstruction filter• ADC Converters– Sampling (continued)• Sampling switch considerations– Thermal noise due to switch resistance– Sampling switch bandwidth limitations– Switch induced distortion• Sampling switch conductance dependence on input voltageEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 4Practical SamplingSummary So Far!22212BBFSCkTV≥()1 for inON o o ox DD thDD thWVgggCVVVVLμ⎛⎞=− = −⎜⎟−⎝⎠0.72sRBfC<<• kT/C noise• Finite RswÆ limited bandwidth• gsw= f (Vin) Æ distortionvINvOUTCM1φ1EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 5Switch On-ResistanceSwitchÆ MOS operating in triode mode:VinCM1φ1ÆVDD() ()()()01,211 is a function of results in distortionWhat if instead of connecting G to a fixed voltage, DSDtriodeDSDtriode ox GS TH DSON DSVONox GS th ox DD th inON indIWVICVVVLRdVRWWCVV CVVVLLRVμμμ→⎛⎞=−− ≅⎜⎟⎝⎠==−−−→a floating and fixed voltage source is connected to G & S?Desirable to maximize on voltage of GS Minimize ONR→EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 6Boosted & Constant VGS SamplingVGS=const.OFFON• Increase gate overdrive voltage as much as possible + keep VGSconstant¾ Switch overdrive voltage independent of signal level¾ Error due to finite RONlinear (to 1st order)¾ Lower RonÆ lower time constantÆ Higher frequency of operation• Gate voltage VGS=low¾ Device off¾ Beware of signal feedthrough due to parasitic capacitorsEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 7Constant VGS Sampling(= voltage @ the switch input terminal)EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 8Constant VGS Sampling CircuitVP1100nsM12M8M9M6M11Vin1.5V1MHzCholdPC1C2M1M2VDD=3VM3C3M5M4PThis Example: All device sizes:10μ/0.35μAll capacitor size: 1pF (except for Chold)Note: Each critical switch requires a separate clock boosterVgVaVbSampling switch & CPBRef: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599. PBEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 9Clock Voltage Doubler OperationC1C2M10ffM2Saturation modeVP1=clockPBVDD=0Æ3VPa) Start–up 0Æ3V0Æ3V0Æ00Æ3V0Æ(3V-VthM2)Acquire chargeC1C2M1Triode M2offVP1PBVDD=3VP3VÆ03VÆ03VÆ0Æ3V(3V-VthM2)Æ(6V-VthM2)b) Next clock transition0Æ3VVP1EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 10Clock Voltage Doubler OperationC1C2M10ffM2VP1PBVDD=3VP0Æ3V0Æ3V3VÆ~6V3VÆ0c) Next clock phase (6V-VthM2)Æ(3V-VthM2)Æ~ 3VM2TriodeAcquires charge• Both C1 & C2 Æ charged to VDD after one clock cycle• Note that bottom plate of C1 & C2 is either 0 or VDD while top plates are at VDD or 2VDDEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 11Clock Voltage DoublerSimulation C1C2M1M2VP1Clock period: 100nsPBP_BoostVDD2VDD0VDD=3VR1 R2*R1 & R2=1GOhmÆ dummy resistors added for simulation onlyPEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 12Constant VGSSampler: Φ Low• Sampling switch M11 is OFF• C3 charged to ~VDDInput voltagesourceM3TriodeC3M12TriodeM4OFFVS11.5V1MHzChold1pF~ 2 VDD(boosted clock)VDDVDDOFFM11OFFDeviceOFFVDD=3VEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 13Constant VGSSampler: Φ High• C3 previously charged to VDD • M8 & M9 are on:C3 across G-S of M11• M11 on with constant VGS = VDDC31pFM8M9M11VS11.5V1MHzChold1pFVDDEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 14Constant VGS SamplingSimulationInput Switch VGateInput SignalChold SignalEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 15Boosted Clock Sampling Complete CircuitRef: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599. Clock MultiplierSwitchM7 & M13 for reliabilityRemaining issues:-VGSconstant only for Vin<Vout-Nonlinearity due to Vth dependence of M11on body-source voltage EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 16Advanced Clock Boosting TechniqueRef: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314Sampling SwitchEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 17Advanced Clock Boosting Technique•clkÆ low– Capacitors C1a & C1b Æ charged to VDD–MS Æ off– Hold modeSampling SwitchclkÆ lowEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 18Advanced Clock Boosting TechniqueSampling Switch•clkÆ high– Top plate of C1a & C1b connected to gate of sampling switch– Bottom plate of C1a connected to VIN– Bottom plate of C1b connected to VOUT– VGS & VGD of MS both @ VDD & ac signal on G of MS Æ average of VIN& VOUTclkÆ highEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling © 2007 H.K. Page 19Advanced Clock Boosting Technique• Gate tracks average of input and output, reduces effect of I·R drop at high frequencies• Bulk also tracks signal ⇒ reduced body effect (technology used allows connecting bulk to S)• Reported measured SFDR = 76.5dB at fin=200MHzRef: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Tech. Papers, pp.
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