Midterm Exam Statistics Number of Occurrence 6 Mean 16 Standard Deviation 2 5 4 3 2 1 0 10 15 EECS 247 Lecture 18 16 17 Nyquist Rate ADCs Sampling 17 5 Grade Max 20 18 2007 H K Page 1 EE247 Lecture 18 ADC Converters Sampling continued Sampling switch considerations Switch induced distortion Sampling switch conductance dependence on input voltage Clock voltage boosters Sampling switch charge injection clock feedthrough Complementary switch Use of dummy device Bottom plate switching Track hold circuits T H circuit incorporating gain offset cancellation EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 2 Summary of Last Lecture DAC Converters continued Dynamic element matching DAC reconstruction filter ADC Converters Sampling continued Sampling switch considerations Thermal noise due to switch resistance Sampling switch bandwidth limitations Switch induced distortion Sampling switch conductance dependence on input voltage EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 3 Practical Sampling Summary So Far kT C noise C 12k BT 1 22 B VFS 2 vIN vOUT M1 Finite Rsw limited bandwidth 0 72 R B f sC C gsw f Vin distortion Vin gON go 1 VDD Vth EECS 247 Lecture 18 for go Cox Nyquist Rate ADCs Sampling W VDD Vth L 2007 H K Page 4 Switch On Resistance Switch MOS operating in triode mode I D triode Cox RON W L VDS VGS VTH 2 dI D triode 1 RON dVDS VDS 1 1 W W Cox VGS Vth Cox VDD Vth Vin L L 1 VDD RON is a function of Vin results in distortion What if instead of connecting G to a fixed voltage a floating and fixed voltage source is connected to G S Desirable to maximize on voltage of GS Minimize RON EECS 247 Lecture 18 VDS 0 Nyquist Rate ADCs Sampling Vin M1 C 2007 H K Page 5 Boosted Constant VGS Sampling VGS const OFF ON Gate voltage VGS low Device off Beware of signal feedthrough due to parasitic capacitors EECS 247 Lecture 18 Increase gate overdrive voltage as much as possible keep VGS constant Switch overdrive voltage independent of signal level Error due to finite RON linear to 1st order Lower Ron lower time constant Higher frequency of operation Nyquist Rate ADCs Sampling 2007 H K Page 6 Constant VGS Sampling voltage the switch input terminal EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 7 Constant VGS Sampling Circuit VDD 3V PB M2 M1 M3 M8 M6 M4 C1 P PB C2 C3 Vg P M5 M12 M9 Va Vin VP1 1 5V 1MHz 100ns Vb M11 Chold This Example All device sizes 10 0 35 Sampling switch C All capacitor size 1pF except for Chold Note Each critical switch requires a separate clock booster Ref A Abo et al A 1 5 V 10 bit 14 3 MS s CMOS Pipeline Analog to Digital Converter JSSC May 1999 pp 599 EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 8 Clock Voltage Doubler Operation VDD 0 3V VDD 3V M2 Saturation mode M1 0ff Acquire charge C2 C1 3V VthM2 6V VthM2 3V 0 3V 0 3V VthM2 0 3V M2 off M1 Triode C2 C1 PB PB 3V 0 0 0 0 3V 0 3V P P VP1 VP1 clock 0 3V 3V 0 VP1 b Next clock transition a Start up EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 9 Clock Voltage Doubler Operation VDD 3V M1 0ff M2 M2 Triode 6V VthM2 3V VthM2 3V 3V 6V Acquires charge C2 C1 PB 0 3V 3V 0 P VP1 0 3V Both C1 C2 charged to VDD after one clock cycle Note that bottom plate of C1 C2 is either 0 or VDD while top plates are at VDD or 2VDD c Next clock phase EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 10 Clock Voltage Doubler Simulation 2VDD VDD 3V M2 M1 R1 P Boost R2 VDD C2 C1 PB P 0 VP1 Clock period 100ns EECS 247 Lecture 18 R1 R2 1GOhm dummy resistors added for simulation only Nyquist Rate ADCs Sampling 2007 H K Page 11 Constant VGS Sampler Low VDD 3V 2 VDD boosted clock VDD M3 Triode OFF Sampling switch M11 is OFF M4 C3 Device OFF VDD M12 Triode OFF M11 OFF VS1 1 5V 1MHz Input voltage source EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Chold 1pF C3 charged to VDD 2007 H K Page 12 Constant VGS Sampler High C3 previously charged to VDD M8 VDD C3 1pF M8 M9 are on C3 across G S of M11 M11 M9 VS1 1 5V 1MHz EECS 247 Lecture 18 Chold 1pF M11 on with constant VGS VDD Nyquist Rate ADCs Sampling 2007 H K Page 13 Constant VGS Sampling Simulation Input Switch VGate Chold Signal Input Signal EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 14 Boosted Clock Sampling Complete Circuit Clock Multiplier M7 M13 for reliability Remaining issues VGS constant only for Vin Vout Nonlinearity due to Vth dependence of M11on bodysource voltage Switch Ref A Abo et al A 1 5 V 10 bit 14 3 MS s CMOS Pipeline Analog to Digital Converter JSSC May 1999 pp 599 EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 15 Advanced Clock Boosting Technique Ref M Waltari et al A self calibrated pipeline ADC with 200MHz IFsampling frontend ISSCC 2002 Dig Tech Papers pp 314 Sampling Switch EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 16 Advanced Clock Boosting Technique clk low Sampling Switch clk low Capacitors C1a C1b charged to VDD MS off Hold mode EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 17 Advanced Clock Boosting Technique clk high clk high Sampling Switch Top plate of C1a C1b connected to gate of sampling switch Bottom plate of C1a connected to VIN Bottom plate of C1b connected to VOUT VGS VGD of MS both VDD ac signal on G of MS average of VIN VOUT EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 18 Advanced Clock Boosting Technique Ref M Waltari et al A self calibrated pipeline ADC with 200MHz IFsampling frontend ISSCC 2002 Dig Tech Papers pp 314 Sampling Switch Gate tracks average of input and output reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect technology used allows connecting bulk to S Reported measured SFDR 76 5dB at fin 200MHz EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 19 Constant Conductance Switch Ref H Pan et al A 3 3 V 12 b 50 MS s A D converter in 0 6um CMOS with over 80 dB SFDR IEEE J Solid State Circuits pp 1769 1780 Dec 2000 EECS 247 Lecture 18 Nyquist Rate ADCs Sampling 2007 H K Page 20 Constant Conductance Switch OFF Ref H Pan et al A 3 3 V 12 b 50 MS s A D converter in 0 6um CMOS with over 80 dB SFDR IEEE J …
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