EE247 Lecture 10 Switched capacitor filters continued DDI integrators LDI integrators Effect of parasitic capacitance Bottom plate integrator topology Switched capacitor resonators Bandpass S C filters Lowpass S C filters Switched capacitor filter design considerations Termination implementation Transmission zero implementation Effect of non idealities Switched capacitor filters utilizing double sampling technique EECS 247 Lecture 10 Switched Capacitor Filters 2010 H K Page 1 DDI Switched Capacitor Integrator Vin 1 Cs 1 CI 1 e j T j Vo z e j T j T 2 Cs j eT 2 j T 2 CI e e sinc e sin e j e j 2j Cs 1 e j T 2 CI 2sin T 2 Cs 1 CI j T Ideal Integrator EECS 247 Lecture 9 1 Cs 1 Vo C C z s z 1 s 1 CI CI 1 z 1 z Vin CI 2 T 2 e j T 2 sin T 2 Magnitude Error Switched Capacitor Filters 2010 H K Page 2 DDI Switched Capacitor Integrator Vin 1 CI 2 1 Cs Vo z Cs 1 CI j T Vin Vo T 2 sin T 2 e j T 2 Example Mag phase error for 1 f fs 1 12 Mag error 1 or 0 1dB Phase error 15 degree Qintg 3 8 2 f fs 1 32 Mag error 0 16 or 0 014dB Phase error 5 6 degree Qintg 10 2 EECS 247 Lecture 9 DDI Integrator magnitude error no problem phase error major problem Switched Capacitor Filters 2010 H K Page 3 5th Order Low Pass Switched Capacitor Filter Built with DDI Integrators j j s s plane Coarse View s plane Fine View s s s EECS 247 Lecture 9 Example 5th Order Elliptic Filter Singularities pushed towards RHP due to integrator excess phase Switched Capacitor Filters Ideal Pole Ideal Zero DDI Pole DDI Zero 2010 H K Page 4 H j Passband Switched Capacitor Filter Build with DDI Integrator Peaking SC DDI based Filter Zeros lost Continuous Time Prototype fs 2 EECS 247 Lecture 9 f 2fs fs Frequency Hz Switched Capacitor Filters 2010 H K Page 5 Switched Capacitor Integrator Output Sampled on 2 Vin 1 CI 2 2 Cs Vo Vo2 Sample output clock cycle earlier Sample output on 2 EECS 247 Lecture 9 Switched Capacitor Filters 2010 H K Page 6 Switched Capacitor Integrator Output Sampled on 2 n 3 2 Ts n 1 Ts 1 2 n 1 2 Ts nTs n 1 2 Ts 1 n 1 Ts 1 2 Clock Vin Vs Vo2 F1 Qs n 1 Ts Cs Vi n 1 Ts QI n 1 Ts QI n 3 2 Ts F2 Qs n 1 2 Ts 0 QI n 1 2 Ts QI n 3 2 Ts Qs n 1 Ts F1 F2 Qs nTs Cs Vi nTs QI nTs QI n 1 Ts Qs n 1 Ts Qs n 1 2 Ts 0 QI n 1 2 Ts QI n 1 2 Ts Qs n Ts EECS 247 Lecture 9 Switched Capacitor Filters 2010 H K Page 7 Switched Capacitor Integrator Output Sampled on 2 n 3 2 Ts 1 n 1 Ts n 1 2 Ts 2 nTs 1 n 1 Ts 2 1 Clock Vin Vs Vo QI n 1 2 Ts QI n 1 2 Ts Qs n Ts Vo2 QI CI Vi Qs Cs CI Vo2 n 1 2 Ts CI Vo2 n 1 2 Ts Cs Vi n Ts Using the z operator rules V o2 z Cs z 1 2 CI 1 z 1 Vin CI Vo2 z1 2 CI Vo2 z 1 2 Cs Vi EECS 247 Lecture 9 Switched Capacitor Filters 2010 H K Page 8 LDI Switched Capacitor Integrator LDI Lossless Discrete Integrator same as DDI but output is sampled clock cycle earlier LDI V o2 z Cs z 1 2 CI 1 z 1 Vin z e Vin 1 CI 2 Cs 2 Vo2 j T j T 2 Cs Cs C e j T C j T 2 1 j T 2 I I 1 e e e Cs 1 jC I 2 si n T 2 Cs 1 C I j T Ideal Integrator EECS 247 Lecture 9 T 2 si n T 2 No Phase Error For signals at frequencies sampling freq Magnitude error negligible Magnitude Error Switched Capacitor Filters 2010 H K Page 9 Switched Capacitor Filter Built with LDI Integrators H j Zeros Preserved fs 2 EECS 247 Lecture 9 fs Frequency Hz Switched Capacitor Filters 2fs f 2010 H K Page 10 Switched Capacitor Integrator Parasitic Capacitor Sensitivity Vin 1 CI 2 Vo Cp2 Cp1 Cs Cp3 Effect of parasitic capacitors 1 Cp3 driven by opamp o k 2 Cp2 at opamp virtual gnd o k 3 Cp1 Charges to Vin discharges into CI Cp1 includes the MOS switch junction capacitors which are voltage dependent not only affects C ratios but results in non linearities Problem parasitic capacitor sensitivity EECS 247 Lecture 9 Switched Capacitor Filters 2010 H K Page 11 Parasitic Insensitive Bottom Plate Switched Capacitor Integrator Sensitive parasitic cap Cp1 rearrange circuit so that Cp1 does not charge discharge 1 1 Cp1 grounded 2 1 Cp1 at virtual ground 1 CI 2 Cs Cp1 Vi Vo Cp2 Vi Solution Bottom plate capacitor integrator EECS 247 Lecture 9 Switched Capacitor Filters 2010 H K Page 12 Bottom Plate Switched Capacitor Integrator 1 1 CI 2 2 Cs Vo Vi Vo1 Vo2 Output Input z Transform Vi Vo1 on 1 Note Different delay from Vi Vi to either output Special attention needed for input output connections to ensure LDI realization EECS 247 Lecture 9 Cs z 1 CI 1 z 1 Vi on 1 Vion 2 1 2 C s z CI 1 z 1 Switched Capacitor Filters Vo2 on 2 1 Cs z 2 1 CI 1 z C s 1 CI 1 z 1 2010 H K Page 13 Bottom Plate Switched Capacitor Integrator z Transform Model 1 1 z z 1 z C1s Vi CI 2 1 z Vi Cs CI Vi Cs CI 2 1 z 1 12 z 1 Input Output z transform 1 1 Vi 1 12 Vo Vo1 Vo2 1 z z 12 1 z 2 1 z 1 Vo1 z 12 Vo2 LDI EECS 247 Lecture 9 Switched Capacitor Filters 2010 H K Page 14 LDI Switched Capacitor Ladder Filter 1 s 3 1 1 s 4 s 5 1 z 2 1 z 1 1 2 1 z 2 1 z 1 1 z 2 1 z 2 C s 1 z 2 1 z 1 z 2 Cs CI CI z 2 1 z 1 C s Cs CI 1 z 2 Cs CI CI C s CI To test whether LDI or DDI Need to examine delay around the integrator loop Delay around integrator loop is z 1 2 z 1 2 1 LDI function EECS 247 Lecture 9 Switched Capacitor Filters 2010 H K Page 15 Switched Capacitor LDI Resonator Resonator Signal Flowgraph 1 s 1 2 2 2 1 s C 1 fs 1 Re q1 C2 C2 C 1 2 fs 3 Re q3 …
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