EECS 247 Lecture 21: Data Converters: Nyquist Rate ADCs © 2010 Page 1Lecture 21Analog-to-Digital Converters (continued)– Residue Type ADCs• Two-Step flash• Pipelined ADCs– Concept and basics of the architecture– Effect of building block non-idealities on overall ADC performance• Sub-ADC • Sub-DAC• Gain stage– Error correction by adding redundancy– Digital calibration– Correction for inter-stage gain nonlinearityEECS 247 Lecture 21: Data Converters- Nyquist Rate ADCs © 2010 Page 2ADC Architectures• Slope type converters• Successive approximation• Flash• Interpolating & Folding • Residue type ADCs– Two-step Flash– Pipelined ADCs– …• Time-interleaved / parallel converter• Oversampled ADCsEECS 247- Lecture 21 Residue Type ADCs © 2010 Page 3Two-Step Example: (2+2)Bits• Using only one ADC: output contains large quantization error• "Missing voltage" or "residue" ( -eq1)• Idea: Use second ADC to quantize and add -eq10 1 2 3000110110 1 2 3-0.50.5[LSB]ADC Input [LSB]Vin+Dout= Vin + eq12-bit ADC 2-bit ADC???eq1DoutVinEECS 247- Lecture 21 Residue Type ADCs © 2010 Page 4Two Stage Example• Use DAC to compute missing voltage• Add quantized representation of missing voltage• Why does this help? How about eq2? • Since maximum voltage at input of the 2ndADC is Vref1/4 then for 2ndADC Vref2=Vref1/4 and thus eq2= eq1/4 =Vref1/16 4bit overall resolutionVin“Coarse“+Dout= Vin+ eq1 2-bit ADC 2-bit ADC“Fine“+-2-bit DAC-eq1-eq1+eq2-eq1+eq2Vref2Vref1EECS 247- Lecture 21 Residue Type ADCs © 2010 Page 5Two Step (2+2) Flash ADCVinVinVin4-bit Straight Flash ADC Ideal 2-step Flash ADCVoltage quantized by 2ndADCEECS 247- Lecture 21 Residue Type ADCs © 2010 Page 6Two Stage Example• Fine ADC is re-used 22times• Fine ADC's full scale range needs to span only 1 LSB of coarse quantizer221222222 refrefqVVe00 01 10 11Vref1/22-eq100011011First ADC“Coarse“Second ADC“Fine“VinVref1Vref2EECS 247- Lecture 21 Residue Type ADCs © 2010 Page 7Two-Stage (2+2) ADC Transfer Function0000000100100011010001010110011110001001101010111100110111101111CoarseBits(MSB)FineBits(LSB)DoutVinVref1EECS 247- Lecture 21 Residue Type ADCs © 2010 Page 8Residue or Multi-Step Type ADCIssues• Operation:– Coarse ADC determines MSBs– DAC converts the coarse ADC output to analog- Residue is found by subtracting (Vin-VDAC)– Fine ADC converts the residue and determines the LSBs– Bits are combined in digital domain • Issue: 1. Fine ADC has to have FS=FScoarse/2B1& precision in the order of overall ADC 1/2LSB 2. Speed penalty Need at least 1 clock cycle per extra series stage to resolve one sample (optional)Coarse ADC(B1-Bit)VinResidueDAC(B1-Bit)Fine ADC(B2-Bit)Bit Combiner(B1+B2)-BitEECS 247- Lecture 21 Residue Type ADCs © 2010 Page 9Solution to Issue (1)Reducing Precision Required for Fine ADC• Accuracy needed for fine ADC relaxed by introducing inter-stage gain– Example: By adding gain of x(G=2B1=4) prior to fine ADC in (2+2)bit case, precision required for fine ADC is reduced to 2-bit only!– Additional advantage- coarse and fine ADC can be identical stagesVin“Coarse“+Dout= Vin+ eq1 2-bit ADC 2-bit ADC“Fine“+-2-bit DAC-eq1-eq1+eq2-eq1+eq2G=2B1EECS 247- Lecture 21 Residue Type ADCs © 2010 Page 10Solution to Issue (2)Increasing ADC Throughput• Conversion time significantly decreased by employing T/H between stages– All stages busy at all times operation concurrent– During one clock cycle coarse & fine ADCs operate concurrently:• First stage samples/converts/generates residue of input signal sample # n• While 2ndstage samples/converts residue associated with sample # n-1Vin“Coarse“+Dout= Vin+ eq1 2-bit ADC2-bit ADC“Fine“+-2-bit DAC-eq1-eq1+eq2T/H+(G=2B1)T/HEECS 247- Lecture 21 Pipelined ADCs © 2010 Page 11Residue Type ADCs• Two-Step flash• Pipelined ADCs– Basic operation– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall ADC performance• Error correction by adding redundancy• Digital calibration• Correction for inter-stage gain nonlinearity– Implementation • Practical circuits• Stage scaling• Combining the bits• Stage implementation– Circuits– Noise budgeting• How many bits per stage?EECS 247- Lecture 21 Pipelined ADCs © 2010 Page 12Pipeline ADCBlock Diagram• Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!)• Each stage performs coarse A/D conversion and computes its quantization error, or "residue“• All stages operate concurrentlyAlign and Combine DataStage 1B1 BitsStage 2B2 BitsDigital output(B1 + B2 + ... + Bk) BitsVinMSB... ...LSB Stage k Bk BitsVres1Vres2EECS 247- Lecture 21 Pipelined ADCs © 2010 Page 13Pipeline ADC Concurrent Stage Operation• Stages operate on the input signal like a shift register• New output data every clock cycle, but each stage introduces at least ½ clock cycle latencyAlign and Combine DataStage 1B1BitsStage 2B2BitsDigital output(B1+ B2 + ... + Bk) BitsVinStage kBkBitsf1f2acquireconvertconvertacquire......CLKf1f2EECS 247- Lecture 21 Pipelined ADCs © 2010 Page 14Pipeline ADCLatency[Analog Devices, AD 9226 12bit ADC Data Sheet]Note: One conversion per clock cycle & 8 clock cycle latencyEECS 247- Lecture 21 Pipelined ADCs © 2010 Page 15Pipelined ADCCharacteristics• Number of components (stages) grows linearly with resolution• Pipelining– Trading latency for overall component count– Latency may be an issue in e.g. control systems– Throughput limited by speed of one stage Fast• Versatile: 8...16bits, 1...400MS/s• One important feature of pipelined ADCs: many analog circuit non-idealities can be corrected digitallyEECS 247- Lecture 21 Pipelined ADCs © 2010 Page 16Pipeline ADCDigital Data Alignment• Digital shift register aligns sub-conversion results in timeStage 2B2BitsVinStage kBkBitsf1f2acquireconvertconvertacquire......+ +DoutCLK CLK CLKStage 1B1BitsCLKf1f2EECS 247- Lecture 21 Pipelined ADCs © 2010 Page 17Cascading More Stages• LSB of last stage becomes very small • All stages need to have full precision• Impractical to generate several VrefVinADC+-DACADCB3bitsB2bitsB1bitsVrefVref /2B1Vref /2(B1+B2)Vref /2(B1+B2+B3)EECS 247- Lecture 21 Pipelined ADCs © 2010 Page 18Pipeline ADC
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