Lecture 21 Analog to Digital Converters continued Residue Type ADCs Two Step flash Pipelined ADCs Concept and basics of the architecture Effect of building block non idealities on overall ADC performance Sub ADC Sub DAC Gain stage Error correction by adding redundancy Digital calibration Correction for inter stage gain nonlinearity EECS 247 Lecture 21 Data Converters Nyquist Rate ADCs 2010 Page 1 ADC Architectures Slope type converters Successive approximation Flash Interpolating Folding Residue type ADCs Two step Flash Pipelined ADCs Time interleaved parallel converter Oversampled ADCs EECS 247 Lecture 21 Data Converters Nyquist Rate ADCs 2010 Page 2 Two Step Example 2 2 Bits 2 bit ADC Dout 11 2 bit ADC Vin Vin 10 01 00 0 Dout Vin eq1 LSB 0 5 eq1 0 5 1 2 3 0 1 2 3 ADC Input LSB Using only one ADC output contains large quantization error eq1 Missing voltage or residue Idea Use second ADC to quantize and add eq1 EECS 247 Lecture 21 Residue Type ADCs 2010 Page 3 Two Stage Example Vref1 Vin eq1 Coarse 2 bit ADC Vref2 Fine 2 bit DAC 2 bit ADC eq1 eq2 Dout Vin e e e q1 q1 q2 Use DAC to compute missing voltage Add quantized representation of missing voltage Why does this help How about eq2 Since maximum voltage at input of the 2nd ADC is Vref1 4 then for 2nd ADC Vref2 Vref1 4 and thus eq2 eq1 4 Vref1 16 4bit overall resolution EECS 247 Lecture 21 Residue Type ADCs 2010 Page 4 Two Step 2 2 Flash ADC 4 bit Straight Flash ADC Ideal 2 step Flash ADC Vin Vin Vin Voltage quantized by 2nd ADC EECS 247 Lecture 21 Residue Type ADCs 2010 Page 5 Two Stage Example eq1 11 V ref1 10 22 Vref1 Vin 01 V ref2 Second ADC Fine 00 00 01 10 11 First ADC Coarse Fine ADC is re used 22 times Fine ADC s full scale range needs to span only 1 LSB of coarse quantizer e q2 EECS 247 Lecture 21 Vref 2 2 2 Residue Type ADCs Vref 1 22 22 2010 Page 6 Two Stage 2 2 ADC Transfer Function Dout 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Coarse Bits MSB EECS 247 Lecture 21 Vref1 Fine Bits LSB Vin Residue Type ADCs 2010 Page 7 Coarse ADC B1 Bit DAC B1 Bit Fine ADC B2 Bit optional Residue B1 B2 Bit Vin Bit Combiner Residue or Multi Step Type ADC Issues Operation Coarse ADC determines MSBs DAC converts the coarse ADC output to analog Residue is found by subtracting Vin VDAC Fine ADC converts the residue and determines the LSBs Bits are combined in digital domain Issue 1 Fine ADC has to have FS FScoarse 2B1 precision in the order of overall ADC 1 2LSB 2 Speed penalty Need at least 1 clock cycle per extra series stage to resolve one sample EECS 247 Lecture 21 Residue Type ADCs 2010 Page 8 Solution to Issue 1 Reducing Precision Required for Fine ADC 2 bit ADC Vin 2 bit DAC Coarse eq1 G 2B1 2 bit ADC Fine eq1 eq2 e e Dout Vin e q1 q1 q2 Accuracy needed for fine ADC relaxed by introducing inter stage gain Example By adding gain of x G 2B1 4 prior to fine ADC in 2 2 bit case precision required for fine ADC is reduced to 2 bit only Additional advantage coarse and fine ADC can be identical stages EECS 247 Lecture 21 Residue Type ADCs 2010 Page 9 Solution to Issue 2 Increasing ADC Throughput 2 bit ADC Vin T H G 2B1 2 bit DAC Coarse eq1 Fine T H Dout Vin e e 2 bit ADC e q1 q1 q2 Conversion time significantly decreased by employing T H between stages All stages busy at all times operation concurrent During one clock cycle coarse fine ADCs operate concurrently First stage samples converts generates residue of input signal sample n While 2nd stage samples converts residue associated with sample n 1 EECS 247 Lecture 21 Residue Type ADCs 2010 Page 10 Residue Type ADCs Two Step flash Pipelined ADCs Basic operation Effect of sub ADC sub DAC gain stage non idealities on overall ADC performance Error correction by adding redundancy Digital calibration Correction for inter stage gain nonlinearity Implementation Practical circuits Stage scaling Combining the bits Stage implementation Circuits Noise budgeting How many bits per stage EECS 247 Lecture 21 Pipelined ADCs 2010 Page 11 Pipeline ADC Block Diagram Vin Stage 1 B1 Bits Vres1 Stage 2 B2 Bits Vres2 MSB Stage k Bk Bits LSB Align and Combine Data Digital output B1 B2 Bk Bits Idea Cascade several low resolution stages to obtain high overall resolution e g 10bit ADC can be built with series of 10 ADCs each 1 bit only Each stage performs coarse A D conversion and computes its quantization error or residue All stages operate concurrently EECS 247 Lecture 21 Pipelined ADCs 2010 Page 12 Pipeline ADC Concurrent Stage Operation f1 f2 Vin CLK acquire convert convert acquire Stage 1 B1 Bits Stage 2 B2 Bits Stage k Bk Bits f1 f2 Align and Combine Data Digital output B1 B2 B k Bits Stages operate on the input signal like a shift register New output data every clock cycle but each stage introduces at least clock cycle latency EECS 247 Lecture 21 Pipelined ADCs 2010 Page 13 Pipeline ADC Latency Note One conversion per clock cycle 8 clock cycle latency Analog Devices AD 9226 12bit ADC Data Sheet EECS 247 Lecture 21 Pipelined ADCs 2010 Page 14 Pipelined ADC Characteristics Number of components stages grows linearly with resolution Pipelining Trading latency for overall component count Latency may be an issue in e g control systems Throughput limited by speed of one stage Fast Versatile 8 16bits 1 400MS s One important feature of pipelined ADCs many analog circuit non idealities can be corrected digitally EECS 247 Lecture 21 Pipelined ADCs 2010 Page 15 Pipeline ADC Digital Data Alignment f1 f2 Vin CLK acquire convert convert acquire Stage 1 B1 Bits Stage 2 B2 Bits Stage k Bk Bits f1 f2 CLK Dout CLK CLK Digital shift register aligns sub conversion results in time EECS 247 Lecture 21 Pipelined ADCs 2010 Page 16 Cascading More Stages Vref Vin B1 bits Vref 2 B1 Vref 2 B1 B2 Vref 2 B1 B2 B3 B2 bits ADC B3 bits DAC ADC LSB of last stage becomes very small All stages need to have full precision Impractical to generate several Vref EECS 247 Lecture 21 Pipelined ADCs 2010 Page 17 Pipeline ADC Inter Stage Gain Elements Vref Vref T H 2B1 Vin B 1 bits ADC Vref Vref T H 2B2 B 2 bits T H 2B3 B 3 bits DAC ADC Practical pipelines by adding inter stage gain use single Vref Precision requirements decrease down the pipe Advantageous for noise matching later power dissipation All stages can operate concurrently Throughput 1sample clock cycle EECS 247 Lecture 21 Pipelined ADCs 2010 Page 18 Complete Pipeline Stage Vin e q1 G Vres B bit ADC B bit …
View Full Document
Unlocking...