EE247 Lecture 15 Administrative issues Midterm exam postponed to Tues Oct 28th o You can only bring one 8x11 paper with your own written notes please do not photocopy o No books class or any other kind of handouts notes calculators computers PDA cell phones o Midterm includes material covered to end of lecture 14 EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 1 EE247 Lecture 15 D A converters Static performance of D As continued Systematic random errors Practical aspects of current switched DACs Segmented current switched DACs DAC dynamic non idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching DAC reconstruction filter EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 2 Summary Last Lecture D A converter architectures Resistor string DAC Serial charge redistribution DAC Parallel charge scaling DAC Combination of resistor string MSB binary weighted charge scaling LSB Current source DAC Unit element Binary weighted Static performance Component matching systematic random errors Component random variations Gaussian pdf INL for both unit element DAC INL DNL for unit element EECS 247 Lecture 15 DNL x2B 2 1 Data Converters DAC Design continued 2008 H K Page 3 DAC INL E2 n 1 INL n 2 N 2B 1 0 5 2 T o f i n d ma x var i a nce n N 2 E2 N 4 d E 2 dn 0 2 Error is maximum at mid scale N 2 1 2B 1 2 w i th N 2B 1 IN L 0 0 0 5 n N 1 INL depends on both DAC resolution element matching While DNL is to first order independent of DAC resolution and is only a function of element matching Ref Kuboki et al TCAS 6 1982 EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 4 Simulation Example 12 Bit converter DNL and INL DNL LSB 1 0 04 0 03 LSB 0 1 500 1000 1500 2000 2500 3000 3500 4000 bin INL LSB 2 1 0 2 0 8 LSB 0 1 500 1000 1500 2000 2500 3000 3500 4000 bin EECS 247 Lecture 15 1 B 12 Random generator used in MatLab 2 Computed INL INLmax 0 32 LSB midscale Why is the results not as expected per our derivation Data Converters DAC Design continued 2008 H K Page 5 INL DNL for Binary Weighted DAC Iout INL same as for unit element DAC DNL depends on transition Example 0 to 1 DNL2 d 2 1 to 2 DNL2 3 d 2 2B 1 Iref 4 Iref 2Iref Iref Consider MSB transition 0111 1000 EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 6 DAC DNL Example 4bit DAC Iout 8 Analog Output Iref I2 I4 8Iref 4Iref 6 I1 2Iref 5 Iref 4 2 0 to 1 DNL2 d ref ref 2 1 to 2 DNL2 3 d ref ref 2 1 I4on I2off I1off 3 DNL depends on transition Example EECS 247 Lecture 15 I4off I2off I1off I8off I4on I2on I1on 7 I8 I8 on I2on I1on I2on I1off I1on Digital Input 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 Data Converters DAC Design continued 2008 H K Page 7 Binary Weighted DAC DNL Worst case transition occurs at mid scale DNL for a 4 Bit DAC 15 2 DNL 2B 1 1 2 2B 1 2 DNL2 2 144244 3 14243 10 0111 1000 2B 2 DNLma x 2B 2 5 INLmax 1 2 2B 1 1 2 DNLmax Example 0 2 4 6 8 10 DAC Output LSB EECS 247 Lecture 15 12 14 B 12 1 DNL 0 64 LSB INL 0 32 LSB Data Converters DAC Design continued 2008 H K Page 8 MOS Current Source Variations Due to Device Matching Effects Id Id1 Id 2 2 Id1 dId Id1 Id 2 Id Id Id2 dId dW L 2 dVth W Id VGS Vth L Current matching depends on Device W L ratio matching Larger device area less mismatch effect Current mismatch due to threshold voltage variations Larger gate overdrive less threshold voltage mismatch effect EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 9 Current Switched DACs in CMOS Iout Iref dId Id dW L W L Switch Array 2d Vth VGS Vth 256 128 64 1 Example 8bit Binary Weighted Advantages Can be very fast Reasonable area for resolution 9 10bits Disadvantages Accuracy depends on device W L Vth matching EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 10 Unit Element versus Binary Weighted DAC Unit Element DAC Binary Weighted DAC DN L DN L 2 2 2 IN L IN L B B 1 2 2 B 1 IN L 2 2 Number of switched elements S 2B S B Key point Significant difference in performance and complexity EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 11 Another Random Run DNL LSB 2 1 DNL and INL of 12 Bit converter 1 0 1 LSB Now by chance worst DNL is mid scale 0 1 2 500 1000 1500 2000 2500 3000 3500 4000 bin Close to statistical result INL LSB 2 1 0 8 0 8 LSB 0 1 500 1000 1500 2000 2500 3000 3500 4000 bin EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 12 10Bit DAC DNL INL Comparison Plots 100 Simulation Runs Overlaid Ref C Lin and K Bult A 10 b 500MSample s CMOS DAC in 0 6 mm2 IEEE Journal of Solid State Circuits vol 33 pp 1948 1958 December 1998 Note 2 EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 13 10Bit DAC DNL INL Comparison Plots RMS for 100 Simulation Runs Ref C Lin and K Bult A 10 b 500MSample s CMOS DAC in 0 6 mm2 IEEE Journal of Solid State Circuits vol 33 pp 1948 1958 December 1998 Note 2 EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 14 DAC INL DNL Summary DAC choice of architecture has significant impact on DNL INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision Results assume uncorrelated random element variations Systematic errors and correlations are usually also important and may affect final DAC performance Ref Kuboki S Kato K Miyakawa N Matsubara K Nonlinearity analysis of resistor string A D converters IEEE Transactions on Circuits and Systems vol CAS 29 no 6 June 1982 p 383 9 EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 15 Unit Element versus Binary Weighted DAC Example B 10 Unit Element DAC Binary Weighted DAC DN L DN L 2 3 2 IN L 2 B 2 B 1 1 6 INL 2 B 2 2 1 16 Number of switched elements S 2B 1 0 24 S B 10 Significant difference in performance and complexity EECS 247 Lecture 15 Data Converters DAC Design continued 2008 H K Page 16 Segmented DAC Combination of Unit Element Binary Weighted Objective …
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