EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 1EE247Lecture 15• Administrative issues Midterm exam postponed to Tues. Oct. 28tho You can only bring one 8x11 paper with your own written notes (please do not photocopy)o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones....o Midterm includes material covered to end of lecture 14EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 2EE247Lecture 15• D/A converters– Static performance of D/As (continued)• Systematic & random errors– Practical aspects of current-switched DACs– Segmented current-switched DACs– DAC dynamic non-idealities– DAC design considerations– Self calibration techniques• Current copiers• Dynamic element matching– DAC reconstruction filterEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 3Summary Last LectureD/A converter architectures:–Resistor string DAC–Serial charge redistribution DAC–Parallel charge scaling DAC–Combination of resistor string (MSB) & binary weighted charge scaling (LSB)–Current source DAC• Unit element• Binary weighted• Static performance–Component matching-systematic & random errors• Component random variations Æ Gaussian pdf • INL for both unit-element DAC: σINL= σεx2B/2-1• DNL for unit-element: σDNL=σεEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 4DAC INL• Error is maximum at mid-scale (N/2):• INL depends on both DAC resolution & element matching σε • WhileσDNL= σε is to first order independent of DAC resolution and is only a function of element matchingRef: Kuboki et al, TCAS, 6/198222E2E22EBINLBn1nNdTo find max. variance: 0dnNnN/24121 2 with N 2 1εεεσσσσσσσ⎛⎞−=×⎜⎟⎝⎠=→= → = ×=−=−0.510(2B-1)0.5/20n/NσINL/σεEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 5Simulation Exampleσε= 1%B = 12Random # generator used in MatLabComputed INL:σINLmax= 0.32 LSB(midscale)Why is the results not as expected per our derivation?500 1000 1500 2000 2500 3000 3500 4000-1012binDNL [LSB]12 Bit converter DNL and INL-0.04 / +0.03 LSB500 1000 1500 2000 2500 3000 3500 4000-1012binINL LSB]-0.2 / +0.8 LSBEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 6INL & DNL for Binary Weighted DAC• INL same as for unit element DAC• DNL depends on transition–Example:0 to 1 ÆσDNL2= σ(dΙ/Ι)21 to 2 ÆσDNL2= 3σ(dΙ/Ι)2• Consider MSB transition: 0111 … Æ 1000 …4 IrefIrefIout2Iref2B-1Iref……………EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 7DAC DNLExample: 4bit DAC0000 0001 0010 0011 0100 0101 0110 0111 1000DigitalInputAnalog Output [Iref]8765432104IrefIrefIout2Iref8IrefI8I4I2I1I2on,I1onI2on,I1offI1on• DNL depends on transition–Example:0 to 1ÆσDNL2= σ(dΙref/Ιref)21 to 2 ÆσDNL2= 3σ(dΙref/Ιref)2I4on,I2off,I1off..........I8off, I4on,I2on,I1onI8on, I4off,I2off,I1offEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 8Binary Weighted DAC DNL()()DNLmaxBINL DNLmaxmax2B12B12DNLB2B/21121 2221 20111... 1000...22εεεεεσσσσσσσσσ−−=≅−≅=−+≅1442 4 4314243• Worst-case transition occurs at mid-scale:•Example:B = 12,σε= 1%ÆσDNL= 0.64 LSBÆσINL= 0.32 LSB2 4 6810 12 14051015DAC Output [LSB]σDNL2/ σε2DNL for a 4-Bit DACEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 9MOS Current Source VariationsDue to Device Matching Effectsd1 d2ddd1d2ddWdthLWGSdthLIII2dI I IIIdI d 2 dVIVV+=−=×=+−Id1Id2• Current matching depends on:- Device W/L ratio matching Æ Larger device area less mismatch effect- Current mismatch due to threshold voltage variations:Æ Larger gate-overdrive less threshold voltage mismatch effectEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 10Current-Switched DACs in CMOSWdthLWdGSthLdI d 2dVIVV=+−IoutIref……Switch Array• Advantages:Can be very fastReasonable area for resolution < 9-10bits• Disadvantages:Accuracy depends on device W/L & Vthmatching256 128 64 ………..…..1Example: 8bit Binary WeightedEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 11Unit Element versus Binary Weighted DACUnit Element DAC Binary Weighted DACNumber of switched elements:Key point: Significant difference in performance and complexity!B222DNL INLB122INLSBσσσεσσε≅=−≅=DNLB122INLBS2σσεσσε=−≅=EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 12“Another” Random Run …Now (by chance) worst DNL is mid-scale.Close to statistical result!500 1000 1500 2000 2500 3000 3500 4000-2-1012binDNL [LSB]DNL and INL of 12 Bit converter-1 / +0.1 LSB, 500 1000 1500 2000 2500 3000 3500 4000-1012binINL [LSB]-0.8 / +0.8 LSBEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 1310Bit DAC DNL/INL ComparisonPlots: 100 Simulation Runs OverlaidRef: C. Lin and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948 - 1958, December 1998.Note: σε=2%EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 1410Bit DAC DNL/INL ComparisonPlots: RMS for 100 Simulation RunsRef: C. Lin and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948 - 1958, December 1998.Note: σε=2%EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2008 H.K. Page 15DAC INL/DNL Summary• DAC choice of architecture has significant impact on DNL• INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision• Results assume uncorrelated random element variations• Systematic errors and correlations are usually also important and may affect final DAC performanceRef: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June
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