EECS 247 Analog-Digital Interface Integrated Circuits © 2006 Instructor: Haideh Khorramabadi UC Berkeley Department ofInstructor’s Technical BackgroundAdministrativeOffice Hours & GradingAnalog-Digital Interface CircuitryMOSFET Maximum ft Evolution versus TimeCMOS Device Evolution Progress from 1975 to 2005Impact of CMOS Scaling on Digital Signal ProcessingAnalog Signal Processing CharacteristicsCost/Function Comparison DSP & AnalogDigitally Assisted Analog CircuitryExample: Digital AudioExample: Typical Dual Mode Cell PhoneAreas Utilizing Analog/Digital Interface CircuitryAreas Utilizing Analog/Digital Interface CircuitryUCB Analog Courses EECS 247 - 240 - 242Material Covered in EE247Introduction to FiltersIntroduction to FiltersIntroduction to FiltersSimplest Filter First-Order RC Filter (LPF1)Poles and ZerosFilter Frequency Response Bode PlotFirst-Order Low-Pass RC Filter Including Parasitics (LPF2)Filter Frequency ResponseDynamic Range & Electronic NoiseAnalog Dynamic RangeFirst Order Filter NoiseResistor NoiseResistor NoiseResistor NoiseFirst Order Filter NoiseFirst Order Filter NoiseLPF1 Output Noise Spectral DensityTotal NoiseTotal NoisekT/C NoiseLow Pass Filter Total Output Noise (LPF1)LPF1 Output NoiseLPF1 Output NoiseAnalog Circuit Dynamic RangeAnalog Circuit Dynamic RangeDynamic Range versus Number of BitsDynamic Range versus Power DissipationNoise SummaryEECS 247 Lecture 1: Introduction © 2006 H.K. Page 1EECS 247Analog-Digital Interface Integrated Circuits© 2006Instructor: Haideh KhorramabadiUC Berkeley Department of Electrical Engineering and Computer SciencesLecture 1: IntroductionEECS 247 Lecture 1: Introduction © 2006 H.K. Page 2Instructor’s Technical Background• Ph.D., EECS department -UC Berkeley 1985, advisor Prof. P.R. Gray– Thesis topic: Continuous-time CMOS high-frequency filters• Industrial background– 11 years at ATT & Bell Laboratories, N.J., in the R&D area as a circuit designer• Circuits for wireline communications: CODECs, ISDN, and DSL including ADCs (nyquist rate & over-sampled), DACs, filters, VCOs• Circuits intended for wireless applications• Fiber-optics circuits– 3 years at Philips Semiconductors, Sunnyvale, CA • Managed a group in the RF IC department- developed ICs for CDMA & analog cell phones– 3 years @ Broadcom Corp. – Director of Analog/RF ICs in San Jose, CA. • Projects: Gigabit-Ethernet, TV tuners, and DSL circuitry– Currently consultant for IC design • Teaching experience– Has taught/co-taught EE247 @ UCB since 2003– Instructor for short courses offered by MEAD Electronics – Adjunct Prof. @ Rutgers Univ., N.J. : Taught a graduate level IC courseEECS 247 Lecture 1: Introduction © 2006 H.K. Page 3Administrative• Course web page: http://inst.eecs.berkeley.edu/~EE247 – Course notes will be uploaded on the course website prior to each class– Homeworks & due dates are posted on the course website– Please visit course website often for announcements• Lectures are webcast mainly for the benefit of students @ UCSC http://webcast.berkeley.edu/courses– Please try to attend the classes live to benefit from direct interactions– Make sure you use the provided microphones when asking questions or commenting in classEECS 247 Lecture 1: Introduction © 2006 H.K. Page 4Office Hours & Grading• Office hours:– Tues./Thurs. 3:30-4:30pm @ 463 Cory Hall (unless otherwise announced in the class) – Extra office hours by appointment– You can also discuss issues via email: [email protected]• Course grading: – Homework/project 50%– Midterm 20% (tentative date: Oct. 24)– Final 30% (Dec. 18)EECS 247 Lecture 1: Introduction © 2006 H.K. Page 5Analog-Digital Interface CircuitryDigitalProcessorAnalog/Digital InterfaceAnalog InputAnalog WorldDigital/AnalogInterface0 0 11 1 00 1 01 0 0 11 0 1 00 0 1 0Analog Output• Naturally occurring signals are analog• To process signals in the digital domain∴ Need Analog/Digital & Digital/Analog interface circuitryQuestion: Why not process the signal with analog circuits only & thus eliminate need for A/D & D/A?EECS 247 Lecture 1: Introduction © 2006 H.K. Page 6MOSFET Maximum ftEvolution versus Time*Ref: Paul R. Gray UCB EE290 course ‘95International Technology Roadmap for Semiconductors, http://public.itrs.netFor MOS (VGS -Vth = 0.5V )75 80 85 90 95 ’00 ‘05 6u3u2u1.5u1u0.8u0.6u0.35u0.25u0.13u0.1u1GHz10GHz100GHzftYear0.18u0.065uEECS 247 Lecture 1: Introduction © 2006 H.K. Page 7CMOS Device EvolutionProgress from 1975 to 2005• Feature sizes ~X1/90• Cut-off frequency ft~X300• Minimum size device area ~1/L2• Number of interconnect layers ~X6EECS 247 Lecture 1: Introduction © 2006 H.K. Page 8Impact of CMOS Scaling on Digital Signal Processing• Direct beneficiary of VLSI technology down scaling• Not sensitive to “analog” noise- has to deal with “0” & “1” signal levels only!• Si Area/function reduced drastically due to– Shrinking of feature sizes– Multi metal levels for interconnections (currently 6 metal level v.s. only 1 in the 1970s)• Enhanced functionality & flexibility• Amenable to automated design & test• “Arbitrary” precision• Provides inexpensive storage capabilityEECS 247 Lecture 1: Introduction © 2006 H.K. Page 9Analog Signal Processing Characteristics• Sensitive to “analog” noise• Has not fully benefited from technology down scaling:– Supply voltages scale down accordingly Æ Reduced voltage swings Æ more challenging analog design– Reduced voltage swings requires lowering of the circuit noise to keep a constant dynamic rangeÆ Higher power dissipation and chip area• Not amenable to automated design • Extra precision comes at a high price• Availability of inexpensive digital capabilities on-chip enables automatic adjustments to compensate for analog circuit impairments• Rapid progress in DSP has imposed higher demands on analog/digital interface circuitryÆ Plenty of room for innovations!EECS 247 Lecture 1: Introduction © 2006 H.K. Page 10Cost/Function ComparisonDSP & Analog• Digital circuitry: Fully benefited from CMOS device scaling– Cost/function decreases by ~29% each yearCost/function X1/30 in 10 years*• Analog circuitry: Not fully benefited from CMOS scaling– Device scaling mandates drop in supply voltagesÆthreaten analog
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