EECS 247- Lecture 24 Oversampled ADCs © 2010 Page 1EE247Lecture 24Oversampled ADCs (continued)• Comparison of limit cycle oscillations 2ndorder vs 1storder SD modulator– 2nd order SD modulator• Practical implementation– Effect of various building block nonidealities on the SD performance• Integrator maximum signal handling capability • Integrator finite DC gain • Comparator hysteresis (minimum signal handling capability)• Integrator non-linearity • Effect of KT/C noise• Finite opamp bandwidth• Opamp slew limited settling– Implementation example–Higher order SD modulators• Cascaded modulators (multi-stage)• Single-loop single-quantizer modulators with multi-order filtering in the forward pathLimit Cycle Oscillation• Issue particular to SD modulator type data converters:–In response to low level DC inputs quantization noise becomes periodic and some of the components could fall with in the passband of interest and thus limit the dynamic range–More pronounced in 1storder SD modulators compared to higher order (e.g. 2ndorder)• Solution: Use dithering (inject noise-like signal at the input ): to randomize quantization noise- If circuit thermal noise is large enough acts as dither- Typically, in the design of SD modulator integrating C values chosen carefully so that inband thermal noise level exceeds quantization noiseEECS 247- Lecture 24 Oversampled ADCs © 2010 Page 2EECS 247- Lecture 24 Oversampled ADCs © 2010 Page 3Limit Cycle Tones in 1stOrder & 2ndOrder SD Modulator• Higher oversampling ratio lower tones• 2ndorder tones much lower compared to 1st• 2X increase in M decreases the tones by 6dB for 1storder loop and 12dB for 2ndorder loopRef: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.R. Gray, “Spectral analysis of quantization noise in a single-loop sigma–delta modulator with dc input,” IEEE Trans. Commun., vol. 37, pp. 588–599, June 1989.6dB12dB2ndOrder SD Modulator1stOrder SD ModulatorInband Quantization noiseEECS 247- Lecture 24 Oversampled ADCs © 2010 Page 4SD ImplementationPractical Design Considerations• Internal node scaling & clipping• Effect of finite opamp gain & nonlinearity• KT/C noise• Opamp noise• Finite opamp bandwidth• Opamp slew limited settling• Effect of comparator nonidealities• Power dissipation considerationsEECS 247- Lecture 24 Oversampled ADCs © 2010 Page 52ndOrder SD ModulatorExample: Switched-Capacitor ImplementationVINDout• Fully differential front-end• Two bottom-plate integrators• 1-bit DAC is made of switches and VrefsEECS 247- Lecture 24 Oversampled ADCs © 2010 Page 6VINDoutDuring phase 1:• 1stintegrator samples Vin on 1ststage C1• 2ndintegrator samples output of 1stintegrator• Comparator senses polarity of 2ndintg. output result saved in output latch• S3 opens prior to S1 minimize effect of charge injectionSwitched-Capacitor Implementation 2ndOrder SDPhase 1EECS 247- Lecture 24 Oversampled ADCs © 2010 Page 7Switched-Capacitor Implementation 2ndOrder SDPhase 2VINDout• Note: S2 connects integrator inputs to + or – Vref, polarity depends on whether Dout is 0 or 1• Input sampled during f1– or + C1xVref transferred to C2 DAC output subtraction & integration EECS 247- Lecture 24 Oversampled ADCs © 2010 Page 8Switched-Capacitor Implementation 2ndOrder SDNodes Scaled for Maximum Dynamic Range• Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (D)• Note: Non-idealities associated with 2ndintegrator and quantizer when referred to the SD input is attenuated by 1stintegrator high gain The only building block requiring low-noise and high accuracy is the 1stintegratorRef: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.EECS 247- Lecture 24 Oversampled ADCs © 2010 Page 92ndOrder SD ModulatorSwitched-Capacitor ImplementationC2=2C1• The ½ loss in front of each integrator implemented by choice of:f0intg=fs /(4p)EECS 247- Lecture 24 Oversampled ADCs © 2010 Page 10Design Phase Simulations• Design of oversampled ADCs requires simulation of extremely long data traces due to the oversampled nature of the system• SPICE type simulators:– Normally used to test for gross circuit errors only – Too slow for detailed performance verification• Typically, behavioral modeling is used in MATLAB-like environments• Circuit non-idealities either computed or found by using SPICE at subcircuit level • Non-idealities introduced in the behavioral model one-by-one first to fully understand the effect of each individually• Next step is to add as many of the non-idealities simultaneously as possible to verify whether there are interaction among non-idealitiesEECS 247- Lecture 24 Oversampled ADCs © 2010 Page 11Testing of AFEAFEData Acq.PC MatlabfsFilteredSinwave• Typically in the design phase, provisions are made to test the AFE separate from Decimator• Output of the AFE (0,1) is acquired by a data acquisition board or logic analyzer • Matlab-like program is used to analyze data e.g. perform filtering & measure SNR, SNDR…..• During pre-silicon design phase, output of AFE is filtered in software & Matlab used to measure SNR, SNDREECS 247- Lecture 24 Oversampled ADCs © 2010 Page 12Example: Testing SD ADC2ndorder SDM=256Note: The Nyquist ADC tests such as INL and DNL test do not apply to SDmodulator type ADCSSD testing is performed via SNDR as a function of input signal levelOverloadPointEECS 247- Lecture 24 Oversampled ADCs © 2010 Page 132ndOrder SDEffect of 1stIntegrator Maximum Signal Handling Capability on SNR1stintegrator maximum signal handling:1.4, 1.5,1.6, and 1.7X D• Effect of 1stIntegrator maximum signal handling capability on converter SNR No SNR loss for max. sig. handling >1.7DRef: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.M=256– Behavioral model – Non-idealities tested one by
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