EE247 Lecture 24 Oversampled ADCs continued Comparison of limit cycle oscillations 2nd order vs 1st order SD modulator 2nd order SD modulator Practical implementation Effect of various building block nonidealities on the SD performance Integrator maximum signal handling capability Integrator finite DC gain Comparator hysteresis minimum signal handling capability Integrator non linearity Effect of KT C noise Finite opamp bandwidth Opamp slew limited settling Implementation example Higher order SD modulators Cascaded modulators multi stage Single loop single quantizer modulators with multi order filtering in the forward path EECS 247 Lecture 24 Oversampled ADCs 2010 Page 1 Limit Cycle Oscillation Issue particular to SD modulator type data converters In response to low level DC inputs quantization noise becomes periodic and some of the components could fall with in the passband of interest and thus limit the dynamic range More pronounced in 1st order SD modulators compared to higher order e g 2nd order Solution Use dithering inject noise like signal at the input to randomize quantization noise If circuit thermal noise is large enough acts as dither Typically in the design of SD modulator integrating C values chosen carefully so that inband thermal noise level exceeds quantization noise EECS 247 Lecture 24 Oversampled ADCs 2010 Page 2 Limit Cycle Tones in 1st Order 2nd Order SD Modulator Higher oversampling ratio lower tones 6dB 1st Order SD Modulator 2nd order tones much lower compared to 1st 2X increase in M decreases the tones by 6dB for 1st order loop and 12dB for 2nd order loop 12dB 2nd Order SD Modulator Inband Quantization noise Ref B P Brandt et al Second order sigma delta modulation for digital audio signal acquisition IEEE Journal of Solid State Circuits vol 26 pp 618 627 April 1991 R Gray Spectral analysis of quantization noise in a single loop sigma delta modulator with dc input IEEE Trans Commun vol 37 pp 588 599 June 1989 EECS 247 Lecture 24 Oversampled ADCs 2010 Page 3 SD Implementation Practical Design Considerations Internal node scaling clipping Effect of finite opamp gain nonlinearity KT C noise Opamp noise Finite opamp bandwidth Opamp slew limited settling Effect of comparator nonidealities Power dissipation considerations EECS 247 Lecture 24 Oversampled ADCs 2010 Page 4 2nd Order SD Modulator Example Switched Capacitor Implementation Dout VIN Fully differential front end Two bottom plate integrators 1 bit DAC is made of switches and Vrefs EECS 247 Lecture 24 Oversampled ADCs 2010 Page 5 Switched Capacitor Implementation 2nd Order SD Phase 1 Dout VIN During phase 1 1st integrator samples Vin on 1st stage C1 2nd integrator samples output of 1st integrator Comparator senses polarity of 2nd intg output result saved in output latch S3 opens prior to S1 minimize effect of charge injection EECS 247 Lecture 24 Oversampled ADCs 2010 Page 6 Switched Capacitor Implementation 2nd Order SD Phase 2 Dout VIN Note S2 connects integrator inputs to or Vref polarity depends on whether Dout is 0 or 1 Input sampled during f1 or C1xVref transferred to C2 DAC output subtraction integration EECS 247 Lecture 24 Oversampled ADCs 2010 Page 7 Switched Capacitor Implementation 2nd Order SD Nodes Scaled for Maximum Dynamic Range Modification gain of in front of integrators reduce optimize required signal range at the integrator outputs 1 7x input full scale D Note Non idealities associated with 2nd integrator and quantizer when referred to the SD input is attenuated by 1st integrator high gain The only building block requiring low noise and high accuracy is the 1st integrator Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 24 Oversampled ADCs 2010 Page 8 2nd Order SD Modulator Switched Capacitor Implementation The loss in front of each integrator implemented by choice of C2 2C1 f0intg fs 4p EECS 247 Lecture 24 Oversampled ADCs 2010 Page 9 Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces due to the oversampled nature of the system SPICE type simulators Normally used to test for gross circuit errors only Too slow for detailed performance verification Typically behavioral modeling is used in MATLAB like environments Circuit non idealities either computed or found by using SPICE at subcircuit level Non idealities introduced in the behavioral model one by one first to fully understand the effect of each individually Next step is to add as many of the non idealities simultaneously as possible to verify whether there are interaction among non idealities EECS 247 Lecture 24 Oversampled ADCs 2010 Page 10 Testing of AFE Typically in the design phase provisions are made to test the AFE separate from Decimator Output of the AFE 0 1 is acquired by a data acquisition board or logic analyzer Matlab like program is used to analyze data e g perform filtering measure SNR SNDR During pre silicon design phase output of AFE is filtered in software Matlab used to measure SNR SNDR fs Filtered Sinwave EECS 247 Lecture 24 AFE Data Acq PC Matlab Oversampled ADCs 2010 Page 11 Example Testing SD ADC Note The Nyquist ADC tests such as INL and DNL test do not apply to SD modulator type ADCS 2nd order SD M 256 SD testing is performed via SNDR as a function of input signal level Overload Point EECS 247 Lecture 24 Oversampled ADCs 2010 Page 12 2nd Order SD Effect of 1st Integrator Maximum Signal Handling Capability on SNR M 256 Behavioral model Non idealities tested one by one 1st integrator maximum signal handling 1 4 1 5 1 6 and 1 7X D Effect of 1st Integrator maximum signal handling capability on converter SNR No SNR loss for max sig handling 1 7D Ref B E Boser et al The Design of Sigma Delta Modulation A D Converters JSSC Dec 1988 EECS 247 Lecture 24 Oversampled ADCs 2010 Page 13 2nd Order SD Effect of 2nd Integrator Maximum Signal Handling Capability on SNR 2nd integrator maximum signal handling 0 75 1 1 25 1 5 and 1 7X D Effect of 2nd Integrator maximum signal handling capability on SNR No SNR loss for max sig handling 1 7 D Ref B E Boser et al The Design of Sigma Delta Modulation A D Converters JSSC Dec 1988 EECS 247 Lecture 24 Oversampled ADCs 2010 Page 14 2nd Order SD Effect of Integrator Finite DC Gain Integrator f1 CI f2 Cs a Vo Vi Cs z 1 CI 1 z 1 1 a z Cs 1 a Cs CI H z Finit DC Gain CI 1 a 1 1 z Cs 1 a CI H DC a H z ideal a opamp gain at DC EECS 247
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