1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Final Exam EECS 247 H. Khorramabadi Tues., Dec. 14, 2010 FALL 2010 Name: SID: Total number of pages:_______________________________________ Score: /60 Problem 1 6 Problem 2 6 Problem 3 10 Problem 4 10 Problem 5 28 Total Score 60point - Closed books and class notes, no calculators/computers/PDAs - Mark all final and intermediate results clearly - Write solutions on the exam sheets. Add extra pages where needed. - Simplify algebraic results as much as possible. - Bring into standard form where applicable, show your work. Useful Expressions: log10 2=0.3, log10 3=0.477, log2 3=0.1.59 2 1/2=1.41 3 1/2=1.732 Problem 1: Consider three ways to use 64 nominally identical 0.1pF capacitors and a single reference voltage to build a DAC with analog full-scale output voltage 0V to Vref. Conversion consists of one initialization cycle followed by one voltage division or charge redistribution cycle. Capacitors may be connected in parallel groups or otherwise to achieve the desired results. Please do not draw every C and switch. Draw only enough number of components to illustrate the concept. Indicate which architecture is sensitive to parasitic capacitor, assuming capacitors have parasitic capacitance only on the bottom plate. Discuss pros and cons of each scheme in terms of performance and complexity of analog and digital circuits required. a- Show a 5-bit DAC using a minimum number of switches. b- Show how to use the capacitors to achieve a 5-bit DAC which is monotonic regardless of any single capacitor ratio error. c- How do we use two identical capacitor arrays plus one additional capacitor Cz , to build a 10-bit DAC with monotonic performance regardless of any single capacitor ratio error?3 Problem 2. A segmented DAC comprises a unit-element MSB DAC with 5 bits and a binary-weight LSB DAC with 4 bits. The MSB and LSB DAC unit-elements are of the same size, however, since the LSB DAC elements are located in the periphery of the lay out array; they tend to have poorer matching compared to MSB DAC elements. The standard deviation of the unit elements associated with the MSB and LSB DACs are 1=1% and 2=31 respectively. a) Find the standard deviation for the maximum overall DAC DNL (DNL). b) For a product yield of 99.7% (3what is the correct number for the DNL to appear in the product date sheet assuming there are no other non-idealities affecting DNL?4 Problem 3: The single stage of a pipelined ADC is shown below. Assume that the sub-DAC is ideal. a) How many comparators does each sub-ADC use? What is the raw number of bits per stage? What is the effective number of bits? b) What is the resolution of a pipelined ADC that uses 9 such stages (the final stage has one less comparator)? What is the overall latency if the stages are designed for minimum delay-per-stage? What is the maximum through-put? c) On the graph paper provided below, plot the residual voltage Vres as a function of the stage input Vin./Vx d) What is the maximum input voltage as a function of Vx for this converter that does not result in overloading? e) What is the maximum tolerable comparator offset? Show your derivation on the graph. f) Draw the block diagram of an ADC that uses three such stages. Indicate how the digital data from each stage must be scaled to obtain the converter output DoutTotal. g) How does offset associated with the last stage comparator affect the converter’s quantization error for the ADC in part (f)? What is the resulting conversion error in terms of LSB for a Vx/4 error in the sub-ADC threshold of the last stage, assuming input full-scale is 2Vx? ADC DAC-DoutVresVin-2Vin/VxDout 01-1-1 10ADC Transfer Function56 Problem 4: The two lines drawn on the graph below indicate the theoretical ideal performance (SQNR) of a low-pass Sigma-Delta ADC with 1-bit digital output to be filtered by a digital filter. a) Based on the dynamic range difference between the two different oversampling ratios, find the order of the Sigma-Delta ADC. In the two cases, the signal bandwidth is kept constant, the sampling frequency is varied. b) Name three architectural approaches for the design of this ADC. c) Choose the architecture which is unconditionally stable and has lower sensitivity to the level of matching of analog/digital blocks. Draw the sampled-data type block diagram. d) Derive the output of the ADC as the function of input signal and quantization noise at the point of insertion. Note that you may have to use extra delay operators as well as differentiators when combining digital outputs to obtain the final output. e) What is the analytical expression for the in-band dynamic range (peak signal-to-quantization noise ratio, SQNR) at the output Y(z) as a function of the oversampling ratio, M=fs/fN? f) Draw the switched-capacitor implementation of the architecture chosen for part c) using bottom-plate type integrators. You can use opamps and comparators & summing circuits at the block diagram level. g) This ADC is intended to be used at the oversampling ratio of 64. The designer claims the capacitor sizes are chosen such that for the oversampling ratio of M=32, the in-band noise level is at -8dB lower compared to theoretical in-band quantization noise. How 0 20 40 60 80 100 120 -100 -80 -60 -40 -20 0 Input Signal Level [dBFS] M=32 M=64 SNDR [dB]7 would the thermal noise affect the SNDR curve associated with M=64? Discuss the derivation and draw the curve on the graph above. h) If the ADC is used at the lower oversampling rate of M=32 do you expect any issues? Explain. What about operating at M=64? i) Modify the graph for a more realistic SNDR curve for input signal levels close to 0dB for the case of M=64. What aspects of the building blocks performance could affect/limit the peak SNDR? j) Assuming the signal bandwidth of interest is 10kHz what is the minimum order for the anti-aliasing prefilter required to suppress the out-of-band signal/s aliasing down to
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