EECS 247 Lecture 20: Data Converters © 2005 H.K. Page 1EE247Lecture 20• ADC Converters– ADC architectures (continued)– Comparator architectures• Latched comparators• Latched comparators incorporating preamplifier• Sample-data comparators– Offset cancellation– Comparator architecture examples– Flash ADC sources of error• Sparkle code• Meta-stabilityEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 2Flash Converter• B-bit flash ADC:– DAC generates all possible 2B-1 levels–2B-1 comparators compare VINto DAC outputs– Comparator output:• If VDAC< VINÆ 0• If VDAC> VINÆ1– Comparator outputs form thermometer code– Encoder converts thermometer to binary codeDigitalOutputVINVREFfsDAC2B-1ÆBEncoderEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 3Flash ADC ConverterExample: 3-bit ConversionEncoderfsThermometer codeB-bitsTimeVREF0011111101VINVINVREFEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 4Flash Converter• Very fast: only 1 clock cycle per conversion– Half cycleÆ VIN & VDAC comparison– Half cycleÆ 2B-1 to B encoding• High complexity: 2B-1 comparators• High capacitance @ input nodeThermometer codeB-bits R/2RRRR/2REncoderDigitalOutputfs.....VINVREFEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 5Folding Converter• Significantly fewer comparators than flash •Fast• Nonidealities in folder limit resolution to ~10-bitsLSBADCMSBADCFolding CircuitVINDigitalOutputEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 6Time Interleaved Converter• Extremely fast:Limited by speed of T/H• Accuracy limited by mismatch in individual ADCs (timing, offset, gain, …)T/H4fsADCfsADC+ T/4ADC+ 2T/4ADC+ 3T/4Serial / Parallel ConversionVINDigital OutputfsfsfsEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 7Residue Type ADC• Quantization error output (“residuum”) enables cascading for higher resolution• Great flexibility for stages: flash, oversampling ADC, …• Optional T/H enables parallelism (pipelining)• Fast: one clock per conversion (with T/H), latencyT/H & Gain(optional)coarse ADC(1 ... 6 Bit)Partial Digital OutputVINErrorDACEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 8Pipelined ADC• Approaches speed of flash, but much lower complexity• One clock per conversion, but K clocks latency• Efficient digital calibration possible• Versatile: from 16Bits / 1MS/s to 14Bits / 100MS/sDigital Correction LogicStage 1B1BitsStage 2B2BitsStage KBkBitsDigital outputup to (B1+ B2+ ... + Bk))BitsVINEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 9Algorithmic ADC• Essentially same as pipeline, but a single stage is used for all partial conversions• K clocks per conversionT/HcoarseADC(1 ... 6 Bit)Digital OutputVINResidueDACShift Register& Correction LogicStartof conversion2BEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 10Oversampled ADC• Hard to comprehend … “easy” to build• Input is oversampled (M times faster than output rate)• Reduces Anti-Aliasing filter requirements and capacitor size• Accuracy independent of component matching• Very high resolution achievable (> 20 Bits)H(z)DigitalDecimationFilterDACVINDigitalOutputfsfs/MEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 11Throughput Rate Comparison100101102103104105024681012141618Clock Cycles per ConversionResolution [Bit]Flash, Pipeline~1 to 2Successive Approximation~B2ndOrder 1-Bit Oversampled ~2(0.4B+1)Serial ~2BEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 12Speed-Resolution Map[www.v-corp.com]EECS 247 Lecture 20: Data Converters © 2005 H.K. Page 13High-Speed A/D Converters• Flash Converter– Comparator design considerations– Binary Encoder• Interpolation• Folding• Pipelined ADCsEECS 247 Lecture 20: Data Converters © 2005 H.K. Page 14Flash Converter• Very fast: only 1 clock cycle per conversion• High complexity: 2B-1 comparators• High input capacitanceR/2RRRR/2REncoderDigitalOutputVINVREFfs.....EECS 247 Lecture 20: Data Converters © 2005 H.K. Page 15Flash ConverterExample: 8-bits ADC•8-bitsÆ 255 comparators•VREF=1V Æ 1LSB=4mV• DNL<1/2LSB ÆComparator input referred offset < 2mV•2mV =6σoffsetÆ σoffset< 0.33mVR/2RRRR/2REncoderDigitalOutputVINVREFfs.....EECS 247 Lecture 20: Data Converters © 2005 H.K. Page 16Flash ADC ConverterExample: 8-bits ADC (continued)Æ1σOffset< 0.33mV• Let us assume in the technology used:– Voffset-per-unit-sqrt(WxL)=5mV– Issues:• Si area quite large• Large input capacitance• Since depending on input voltage different number of comparator input transistors would be on/off- input capacitance varies as input variesÆ Nonlinear input capacitance could give rise to signal distortion20250.33 2302Assuming: 5 / 7653Total input capacitance: 255 0.765 195 !ffsetox GS oxmVVmVWLWLCfF C CWL fFpFμμ== →×=×=→=×=→×=Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433 - 1439, October 1989.EECS 247 Lecture 20: Data Converters © 2005 H.K. Page 17Flash ADC ConverterExample (continued)Trade-offs:– Allowing larger DNL of 1LSB instead of 0.5LSB:• Increases the maximum allowable input-referred offset voltage by a factor of 2• Decreases the required device WxL by a factor of 4• Reduces the input device area by a factor of 4• Reduces the input capacitance by a factor of 4!– Reducing the ADC resolution by 1-bit• Increases the maximum allowable input-referred offset voltage by a factor of 2• Decreases the required device WxL by a factor of 4• Reduces the input device area by a factor of 4• Reduce the input capacitance by a factor of 4EECS 247 Lecture 20: Data Converters © 2005 H.K. Page 18Flash ConverterComparator Maximum Offset versus ADC Resolution10-111010246810VREF=1VVREF=2VAssumption: DNL=0.5LSBNote:Depending on min acceptable yield, numbers associated with 2σ to 7σ offset voltageADC ResolutionMaximum Comparator Voffset[mV]EECS 247 Lecture 20: Data Converters © 2005 H.K. Page 19Voltage ComparatorsFunction: compare the instantaneous value of two analog signalsImportant features:• Maximum clock rate fs Æ settling time, slew rate, small signal bandwidth• ResolutionÆ gain, offset• Overdrive recovery• Input capacitance (and linearity of input capacitance!)• Power dissipation• Common-mode rejection• Kickback noise•…+Vin-+-Vout (Digital
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