EE247 Lecture 20 ADC Converters ADC architectures continued Comparator architectures Latched comparators Latched comparators incorporating preamplifier Sample data comparators Offset cancellation Comparator architecture examples Flash ADC sources of error Sparkle code Meta stability EECS 247 Lecture 20 Data Converters 2005 H K Page 1 Flash Converter B bit flash ADC DAC generates all possible 2B 1 levels 2B 1 comparators compare VIN to DAC outputs Comparator output If VDAC VIN 0 If VDAC VIN 1 VREF D A C VIN fs 2B 1 B Encoder Digital Output Comparator outputs form thermometer code Encoder converts thermometer to binary code EECS 247 Lecture 20 Data Converters 2005 H K Page 2 VIN Flash ADC Converter Example 3 bit Conversion Thermo VIN VREF VREF me t code er fs 0 0 B bits 1 1 0 Encoder 1 1 1 1 1 Time EECS 247 Lecture 20 Data Converters 2005 H K Page 3 Flash Converter VIN Half cycle VIN VDAC comparison Half cycle 2B 1 to B encoding High complexity 2B 1 comparators fs R 2 R R Encoder Very fast only 1 clock cycle per conversion VREF Digital Output R R B bits High capacitance input node EECS 247 Lecture 20 Data Converters R 2 Thermometer code 2005 H K Page 4 Folding Converter MSB ADC VIN Digital Output LSB ADC Folding Circuit Significantly fewer comparators than flash Fast Nonidealities in folder limit resolution to 10 bits EECS 247 Lecture 20 Data Converters 2005 H K Page 5 fs T H ADC fs T 4 Extremely fast Limited by speed of T H ADC fs 2T 4 ADC Accuracy limited by mismatch in individual ADCs timing offset gain EECS 247 Lecture 20 Data Converters fs 3T 4 Digital Output VIN 4fs Serial Parallel Conversion Time Interleaved Converter ADC 2005 H K Page 6 Residue Type ADC Partial Digital Output VIN Error coarse ADC 1 6 Bit DAC T H Gain optional Quantization error output residuum enables cascading for higher resolution Great flexibility for stages flash oversampling ADC Optional T H enables parallelism pipelining Fast one clock per conversion with T H latency EECS 247 Lecture 20 Data Converters 2005 H K Page 7 Pipelined ADC VIN Stage 1 B1 Bits Stage 2 B2 Bits Stage K Bk Bits Digital Correction Logic Digital output up to B1 B2 Bk Bits Approaches speed of flash but much lower complexity One clock per conversion but K clocks latency Efficient digital calibration possible Versatile from 16Bits 1MS s to 14Bits 100MS s EECS 247 Lecture 20 Data Converters 2005 H K Page 8 Algorithmic ADC Start of conversion VIN Digital Output Shift Register Correction Logic coarse ADC 2B DAC T H 1 6 Bit Residue Essentially same as pipeline but a single stage is used for all partial conversions K clocks per conversion EECS 247 Lecture 20 Data Converters 2005 H K Page 9 Oversampled ADC fs VIN fs M Digital Decimation Filter H z Digital Output DAC Hard to comprehend easy to build Input is oversampled M times faster than output rate Reduces Anti Aliasing filter requirements and capacitor size Accuracy independent of component matching Very high resolution achievable 20 Bits EECS 247 Lecture 20 Data Converters 2005 H K Page 10 Resolution Bit 16 14 12 10 8 B 1 Flash Pipeline 1 to 2 18 Su ce ss Appcro 2 nd ximivaeti Ov Or on B ers der am 1ple Bit d 2 0 4 Throughput Rate Comparison B S al eri 2 6 4 2 0 0 10 1 10 2 10 3 10 4 10 5 10 Clock Cycles per Conversion EECS 247 Lecture 20 Data Converters 2005 H K Page 11 Speed Resolution Map www v corp com EECS 247 Lecture 20 Data Converters 2005 H K Page 12 High Speed A D Converters Flash Converter Comparator design considerations Binary Encoder Interpolation Folding Pipelined ADCs EECS 247 Lecture 20 Data Converters 2005 H K Page 13 Flash Converter VREF Very fast only 1 clock cycle per conversion VIN fs R 2 R High input capacitance R Encoder High complexity 2B 1 comparators Digital Output R R R 2 EECS 247 Lecture 20 Data Converters 2005 H K Page 14 Flash Converter Example 8 bits ADC VREF 8 bits 255 comparators VIN fs R 2 R VREF 1V 1LSB 4mV DNL 1 2LSB Comparator input referred offset 2mV Encoder R Digital Output R R 2mV 6 offset R 2 offset 0 33mV EECS 247 Lecture 20 Data Converters 2005 H K Page 15 Flash ADC Converter Example 8 bits ADC continued 1 Offset 0 33mV Let us assume in the technology used Voffset per unit sqrt WxL 5mV V0 ffset 5mV 0 33mV W L W L 230 2 2 CGS CoxW L 765 fF 3 Total input capacitance 255 0 765 195 pF Assuming Cox 5 fF 2 Issues Si area quite large Large input capacitance Since depending on input voltage different number of comparator input transistors would be on off input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion Ref M J M Pelgrom A C J Duinmaijer and A P G Welbers Matching properties of MOS transistors IEEE Journal of Solid State Circuits vol 24 pp 1433 1439 October 1989 EECS 247 Lecture 20 Data Converters 2005 H K Page 16 Flash ADC Converter Example continued Trade offs Allowing larger DNL of 1LSB instead of 0 5LSB Increases the maximum allowable input referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduces the input capacitance by a factor of 4 Reducing the ADC resolution by 1 bit Increases the maximum allowable input referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduce the input capacitance by a factor of 4 EECS 247 Lecture 20 Data Converters 2005 H K Page 17 Flash Converter Assumption DNL 0 5LSB Note Depending on min acceptable yield numbers associated with 2 to 7 offset voltage Maximum Comparator Voffset mV Comparator Maximum Offset versus ADC Resolution 102 VREF 2V 10 VREF 1V 1 10 1 4 EECS 247 Lecture 20 Data Converters 6 8 ADC Resolution 10 2005 H K Page 18 Voltage Comparators Vin Vout Digital Output Function compare the instantaneous value of two analog signals Important features Maximum clock rate fs settling time slew rate small signal bandwidth Resolution gain offset Overdrive recovery Input capacitance and linearity of input capacitance Power dissipation Common mode rejection Kickback noise EECS 247 Lecture 20 Data Converters 2005 H K Page 19 Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input single ended large swing output Output swing compatible with driving digital logic circuits Open loop amplification no frequency compensation required Precise gain not required Latched comparators in response to a strobe input stage disabled digital output stored in
View Full Document
Unlocking...