EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 1Administrative• No office hour on Thurs. this week• Instead, office hour 3 to 4pm on Wed.EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 2EE247Lecture 20ADC Converters– Sampling (continued)• Effect of clock jitter on sampling– ADC architectures and design • Serial- slope type• Successive approximation•Flash• Flash ADC sources of error– Sparkle code– Meta-stability– Comparator designEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 3Summary Last LectureADC Converters– Sampling (continued)• Sampling switch charge injection & clock feedthrough– Complementary switch– Use of dummy device– Bottom-plate switching– Track & hold • Flip-around T/H circuit• T/H combined with summing/difference function• T/H circuit incorporating gain & offset cancellation• T/H aperture uncertaintyEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 4Effect of Clock Jitter• So far assumption was that the clock signal controlling the sampling instants has no variability and have their edges spaced exactly equal to Ts /2• In practice the clock edges are not prefectly spaced and have some level of jitter• Variability in Tscauses errors in data converter performance – "Aperture Uncertainty" or "Aperture Jitter„• Question: for a given application how much clock jitter can be tolerated?EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 5Clock Jitter• Sampling jitter adds an error voltage proportional to the product of (tJ-t0) and the derivative of the input signal at the sampling instant• Jitter doesn’t matter when sampling dc signals (x’(t0)=0)nominal (ideal) samplingtime t0actualsamplingtime tJx(t)x’(t0)EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 6Clock Jitter• The error voltage isnominalsamplingtime t0actualsamplingtime tJx(t)x’(t0)e = x’(t0)(tJ –t0)errorEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 7Jitter ExampleSinusoidal input:Worst case error:0.5 ps0.8 ps0.3 ps10 MHz100 MHz1000 MHz161210dt <<fs# of Bits()()xxxxxmaxmaxxAmplitude: AFrequency: f Jitter: dtx( t ) A s i n 2 f tx'(t ) 2 f Acos 2 f tx'(t ) 2 f AThus:e( t ) x' ( t ) d te( t ) 2 f A d tπππππ==≤≤≤sFSxFSB1BsfAAf22Ae( t )221dt2fπ+==Δ<< ≅<<EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 8Law of Jitter• The worst case looks pretty stringent …what about the “average”?• Let’s calculate the mean squared jitter error (variance)• If we’re sampling a sinusoidal signal x(t) = Asin(2πfxt), then– x’(t) = 2πfxAcos(2πfxt)–E{[x’(t)]2} = 2π2fx2A2• Assume the jitter has variance E{(tJ-t0)2} = τ2EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 9Law of Jitter• If x’(t) and the jitter are independent– E{[x’(t)(tJ-t0)]2}= E{[x’(t)]2} E{(tJ-t0)2}• Hence, the jitter error power is• If the jitter is uncorrelated from sample to sample, this “jitter noise” is whiteE{e2} = 2π2fx2A2τ2EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 10Law of Jitter()τπτπτπxxxffAfADR2log202122/1022222222jitter−===Example:ENOB=12bitfin=35MHz⇒ τ<1ps rms !EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 11Clock Jitter Conclusion• The first requirement is to have a good enough clock generator• Clock signal should be handled carefully on-chip to prevent additional excessive jitter • Usually, clock jitter in the single-digit pico-second range can be prevented by appropriate design techniques:– Separate supplies– Separate analog and digital clocks– Short inverter chains between clock source and destination• Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter:– RMS noise proportional to input frequency– RMS noise proportional to input amplitudeÆIn cases where clock jitter limits the dynamic range, it’s easy to tell, but may be difficult to fix...EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 12ADC Architecture & DesignEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 13ADC Architectures• Slope type converters• Successive approximation•Flash• Time-interleaved / parallel converter• Folding• Residue type ADCs–Two-step–Pipeline–…• Oversampled ADCsEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 14Conversion RateResolutionOversampled & Serial Algorithmice.g. Succ. Approx.Subranginge.g. PipelinedFolding & InterpolativeParallel & Time InterleavedVarious ADC ArchitecturesResolution/Conversion RateEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 15Serial ADCSingle Slope• Counter starts counting @ VRamp=0• Counter stops counting for VIN=VRampÆ Counter output proportional to VINRampGeneratorTimeVRampVRampVIN"0"CounterstopstartClockB1………..BN………..EECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 16Single Slope ADC• Advantages:– Low complexity & simple– INL depends on ramp linearity & not component matching– Inherently monotonic• Disadvantages:–Slow (2Nclock pulses for N-bit conversion) (e.g. N=16 fclock=1MHz Æ needs 65000x1μs=65ms/conversion)– Hard to generate precise ramp required for high resolution ADCs– Need to calibrate ramp slope versus VIN• Better: Dual Slope, Multi-SlopeEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 17Serial ADCDual Slope• First: VINis integrated for a fixed time (2NxTCLK)Æ Vo= 2NxTCLKVIN/τintg•Next: Vois de-integrated with VREFuntil Vo=0Æ Counter output = 2NVIN /VREFIntegratorFlipFlopVoVIN"0"Counter& TimingClockB1………..BN………..-VREFEECS 247 Lecture 20 Nyquist Rate ADC: Architecture & Design © 2007 H.K. Page 18Dual Slope
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