Administrative No office hour on Thurs this week Instead office hour 3 to 4pm on Wed EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 1 EE247 Lecture 20 ADC Converters Sampling continued Effect of clock jitter on sampling ADC architectures and design Serial slope type Successive approximation Flash Flash ADC sources of error Sparkle code Meta stability Comparator design EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 2 Summary Last Lecture ADC Converters Sampling continued Sampling switch charge injection clock feedthrough Complementary switch Use of dummy device Bottom plate switching Track hold Flip around T H circuit T H combined with summing difference function T H circuit incorporating gain offset cancellation T H aperture uncertainty EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 3 Effect of Clock Jitter So far assumption was that the clock signal controlling the sampling instants has no variability and have their edges spaced exactly equal to Ts 2 In practice the clock edges are not prefectly spaced and have some level of jitter Variability in Ts causes errors in data converter performance Aperture Uncertainty or Aperture Jitter Question for a given application how much clock jitter can be tolerated EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 4 Clock Jitter Sampling jitter adds an error voltage proportional to the product of tJ t0 and the derivative of the input signal at the sampling instant x t actual sampling time tJ x t0 Jitter doesn t matter when sampling dc signals x t0 0 EECS 247 Lecture 20 nominal ideal sampling time t0 Nyquist Rate ADC Architecture Design 2007 H K Page 5 Clock Jitter The error voltage is x t actual sampling time tJ e x t0 tJ t0 x t0 error nominal sampling time t0 EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 6 Jitter Example Worst case error Sinusoidal input Ampl i t ude Fr equency Ji t t er A fx dt x t A s i n 2 f xt x t 2 f x Acos 2 f xt x t max 2 f x A Thus e t x t max dt e t 2 f x A dt EECS 247 Lecture 20 A AF S e t dt f x fs 2 2 2 AF S 2B 1 1 B 2 fs of Bits fs dt 16 12 10 10 MHz 100 MHz 1000 MHz 0 5 ps 0 8 ps 0 3 ps Nyquist Rate ADC Architecture Design 2007 H K Page 7 Law of Jitter The worst case looks pretty stringent what about the average Let s calculate the mean squared jitter error variance If we re sampling a sinusoidal signal x t Asin 2 fxt then x t 2 fxAcos 2 fxt E x t 2 2 2fx2A2 Assume the jitter has variance E tJ t0 2 2 EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 8 Law of Jitter If x t and the jitter are independent E x t tJ t0 2 E x t 2 E tJ t0 2 Hence the jitter error power is E e2 2 2fx2A2 2 If the jitter is uncorrelated from sample to sample this jitter noise is white EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 9 Law of Jitter DR jitter A2 2 2 2 f x2 A2 2 1 2 2 f x2 2 20 log10 2 f x Example ENOB 12bit fin 35MHz 1ps rms EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 10 Clock Jitter Conclusion The first requirement is to have a good enough clock generator Clock signal should be handled carefully on chip to prevent additional excessive jitter Usually clock jitter in the single digit pico second range can be prevented by appropriate design techniques Separate supplies Separate analog and digital clocks Short inverter chains between clock source and destination Few if any other analog to digital conversion non idealities have the same symptoms as sampling jitter RMS noise proportional to input frequency RMS noise proportional to input amplitude In cases where clock jitter limits the dynamic range it s easy to tell but may be difficult to fix EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 11 ADC Architecture Design EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 12 ADC Architectures Slope type converters Successive approximation Flash Time interleaved parallel converter Folding Residue type ADCs Two step Pipeline Oversampled ADCs EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 13 Resolution Various ADC Architectures Resolution Conversion Rate Oversampled Serial Algorithmic e g Succ Approx Subranging e g Pipelined Folding Interpolative Parallel Time Interleaved Conversion Rate EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 14 Serial ADC Single Slope VRamp VRamp Ramp Generator B1 BN VIN stop start 0 Counter Clock Time Counter starts counting VRamp 0 Counter stops counting for VIN VRamp Counter output proportional to VIN EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 15 Single Slope ADC Advantages Low complexity simple INL depends on ramp linearity not component matching Inherently monotonic Disadvantages Slow 2N clock pulses for N bit conversion e g N 16 fclock 1MHz needs 65000x1 s 65ms conversion Hard to generate precise ramp required for high resolution ADCs Need to calibrate ramp slope versus VIN Better Dual Slope Multi Slope EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 16 Serial ADC Dual Slope B1 BN VIN Integrator Vo 0 Counter Timing VREF Clock Flip Flop First VIN is integrated for a fixed time 2NxTCLK Vo 2NxTCLK VIN intg Next Vo is de integrated with VREF until Vo 0 Counter output 2N VIN VREF EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 17 Dual Slope ADC o Sl pe V IN Sl op e Co ns t http www maxim ic com appnotes cfm appnote number 1041 Integrate Vin for fixed time TINT de integrate with VREF applied TDe Int 2NxTCLKxVin VREF Most laboratory DVMs use this type of ADC EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 18 Dual Slope ADC Advantage Accuracy to 1st order independent of integrator time constant and clock period Comparator offset referred to input is attenuated by integrator high DC gain Insensitive to most linear error sources DNL is a function of clock jitter Power line 60Hz xtalk effect on reading can be canceled by choosing conversion time multiple of 1 60Hz High accuracy achievable 16 bit Disadvantage Slow maximum 2x2NxTclk per conversion Integrator opamp offset results in ADC offset can cancel Finite opamp gain gives rise to INL EECS 247 Lecture 20 Nyquist Rate ADC Architecture Design 2007 H K Page 19 Successive Approximation ADC SAR Algorithmic type ADC Based on binary search over DAC output Reset DAC Set DAC MSB 1 VIN T H 1 MSB
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