EECS 247 Lecture 18: Data Converters © 2006 H.K. Page 1EE247Lecture 18• Administrative issues Midterm exam Tues. Oct. 31sto You can only bring one 8x11 paper with your own written notes (please do not photocopy)o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones....o Midterm includes material covered to end of lecture 14EECS 247 Lecture 18: Data Converters © 2006 H.K. Page 2EE247Lecture 18• DAC Converters (continued)– DAC reconstruction filter• ADC Converters–Sampling• Sampling switch induced distortion– Sampling switch conductance dependence on input voltage• Sampling switch charge injection– Complementary switch– Use of dummy device– Bottom-plate switchingEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 3Summary of Last LectureDAC Converters (continued)• DAC dynamic non-idealities• DAC design considerations–Common centroid current source layout–INL improvement by non-sequential current source switching • Self calibration techniques–Current copiers–Dynamic element matchingEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 4Example: State-of-the-Art current steering DAC6bit unit-element 8bit binaryEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 5EECS 247 Lecture 18: Data Converters © 2006 H.K. Page 6DAC In the Big Picture• Learned to build DACs– Convert the incoming digital signal to analog• DAC output Æstaircase form• Some applications require filtering (smoothing) of DAC output Æ reconstruction filterAnalog Post processingD/AConversionDSPA/D ConversionAnalog PreprocessingAnalog InputAnalog Output000...001...110Anti-AliasingFilterSampling+Quantization"Bits to Staircase"Reconstruction FilterEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 7DAC Reconstruction Filter• Need for and requirements depend on application• Tasks:– Correct for sinc droop– Remove “aliases”(stair-case approximation)B fs/20 0.5 1 1.5 2 2.5 3x 10600.51DAC Input0 0.5 1 1.5 2 2.5 3x 10600.51sinc0 0.5 1 1.5 2 2.5 300.51DAC OutputNormalized Frequencyf/fsEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 8Reconstruction Filter Options• Digital and SC filter possible only in combination with oversampling (signal bandwidth B << fs/2)• Digital filter– Band limits the input signal Æ prevent aliasing– Could also provide high-frequency pre-emphasis to compensate in-band sinc amplitude droop associated with the inherent DAC S/H functionDigitalFilterDACSCFilterCTFilterReconstruction FiltersEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 9DAC Reconstruction Filter Example: Voice-Band CODEC Receive PathRef: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,” IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.Note: fsigmax = 3.4kHzfsDAC = 8kHzÆsin(π fsigmax x Ts )/(π fsigmax xTs )= -2.75 dB droop due to DAC sinc shapeReceive Outputfs= 8kHzfs= 128kHzfs= 8kHzfs= 128kHzfs= 128kHzGSRReconstruction Filter& sinx/x CompensatorEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 10SummaryD/A Converter • D/A architecture – Unit element – complexity proportional to 2B- excellent DNL – Binary weighted- complexity proportional to B- poor DNL– Segmented- unit element MSB(B1)+ binary weighted LSB(B2)Æ complexity proportional ((2B1-1) + B2) -DNL compromise between the two• Static performance– Component matching• Dynamic performance– Time constants, Glitches• DAC improvement techniques – Symmetrical switching rather than sequential switching– Current source self calibration– Dynamic element matching• Depending on the application, reconstruction filter may be neededEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 11What Next?• ADC Converters:– Need to build circuits that "sample“– Need to build circuits for amplitude quantizationAnalog Post processingD/AConversionDSPA/D ConversionAnalog PreprocessingAnalog InputAnalog Output000...001...110Anti-AliasingFilterSampling+Quantization"Bits to Staircase"Reconstruction FilterEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 12Analog-to-Digital Converters• Two categories:– Nyquist rate ADCs Æ fsigmax~ 0.5xfsampling• Maximum achievable signal bandwidth higher compared to oversampled type• Resolution limited to max. 12-14bits– Oversampled ADCs Æ fsigmax<< 0.5xfsampling• Maximum possible signal bandwidth lower compared nyquist• Maximum achievable resolution high (18 to 20bits!)EECS 247 Lecture 18: Data Converters © 2006 H.K. Page 13MOS Sampling CircuitsEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 14Ideal Sampling• In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage vINonto the capacitor CÆ Output Dirac-like pulses with amplitude equal to VINat the time of sampling• In practice not realizable!vINvOUTCS1φ1φ1T=1/fSEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 15Ideal T/H SamplingvINvOUTCS1φ1•Vouttracks input when switch is closed• Grab exact value of Vinwhen switch opens• "Track and Hold" (T/H) (often called Sample & Hold!)φ1T=1/fSEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 16Ideal T/H SamplingContinuousTimeT/H signal(Sampled-DataSignal)ClockDiscrete-TimeSignaltimeTrackHoldEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 17Practical SamplingIssuesvINvOUTCM1φ1• Switch induced noise power due to M1 finite channel resistance• Finite RswÆ limited bandwidth Æ finite acquisition time•Rsw= f(Vin) Æ distortion• Switch charge injection & clock feedthrough• Clock jitterEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 18kT/C Noise• Switch resistance & sampling capacitor form a low-pass filter • Noise associated with the switch resistance results in Æ Total noise variance= kT/C @ the output (see noise analysis in Lecture 1)• In high resolution ADCs kT/C noise often dominates overall minimum signal handling capability (power dissipation considerations).vINvOUTCS1RvINvOUTCM1φ14kTRΔfEECS 247 Lecture 18: Data Converters © 2006 H.K. Page 19Sampling Network kT/C NoiseFor ADCs sampling capacitor size is usually chosen based on having thermal noise smaller or equal to quantization noise:Assumption: Æ Nyquist rate ADC22222212121212noise Q than equal)(or less is level noise thermalsuch that C Choose12 power noiseon quantizati Total :ADC
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