EE247 Lecture 18 Administrative issues Midterm exam Tues Oct 31st o You can only bring one 8x11 paper with your own written notes please do not photocopy o No books class or any other kind of handouts notes calculators computers PDA cell phones o Midterm includes material covered to end of lecture 14 EECS 247 Lecture 18 Data Converters 2006 H K Page 1 EE247 Lecture 18 DAC Converters continued DAC reconstruction filter ADC Converters Sampling Sampling switch induced distortion Sampling switch conductance dependence on input voltage Sampling switch charge injection Complementary switch Use of dummy device Bottom plate switching EECS 247 Lecture 18 Data Converters 2006 H K Page 2 Summary of Last Lecture DAC Converters continued DAC dynamic non idealities DAC design considerations Common centroid current source layout INL improvement by non sequential current source switching Self calibration techniques Current copiers Dynamic element matching EECS 247 Lecture 18 Data Converters 2006 H K Page 3 Example Stateof the Art current steering DAC 6bit unit element 8bit binary EECS 247 Lecture 18 Data Converters 2006 H K Page 4 EECS 247 Lecture 18 Data Converters 2006 H K Page 5 DAC In the Big Picture Analog Input Learned to build DACs Convert the incoming digital signal to analog DAC output staircase form Some applications require filtering smoothing of DAC output reconstruction filter EECS 247 Lecture 18 Data Converters Analog Preprocessing A D Conversion DSP Anti Aliasing Filter Sampling Quantization 000 001 110 D A Conversion Bits to Staircase Analog Post processing Reconstruction Filter Analog Output 2006 H K Page 6 DAC Reconstruction Filter Need for and requirements depend on application DAC Input B fs 2 1 0 5 0 0 0 5 1 1 5 2 2 5 sinc 1 Correct for sinc droop Remove aliases stair case approximation x 10 0 5 0 DAC Output Tasks 3 6 0 0 5 1 1 5 2 2 5 1 3 6 x 10 0 5 0 0 0 5 1 1 5 2 2 5 Normalized Frequency EECS 247 Lecture 18 Data Converters 3 f fs 2006 H K Page 7 Reconstruction Filter Options Reconstruction Filters Digital Filter DAC SC Filter CT Filter Digital and SC filter possible only in combination with oversampling signal bandwidth B fs 2 Digital filter Band limits the input signal prevent aliasing Could also provide high frequency pre emphasis to compensate in band sinc amplitude droop associated with the inherent DAC S H function EECS 247 Lecture 18 Data Converters 2006 H K Page 8 DAC Reconstruction Filter Example Voice Band CODEC Receive Path Receive Output fs 8kHz fs 8kHz fs 128kHz fs 128kHz Reconstruction Filter sinx x Compensator GSR fs 128kHz Note fsigmax 3 4kHz fsDAC 8kHz sin fsigmax x Ts fsigmax xTs 2 75 dB droop due to DAC sinc shape Ref D Senderowicz et al A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip IEEE Journal of Solid State Circuits Vol SC 17 No 6 pp 1014 1023 Dec 1982 EECS 247 Lecture 18 Data Converters 2006 H K Page 9 Summary D A Converter D A architecture Unit element complexity proportional to 2B excellent DNL Binary weighted complexity proportional to B poor DNL Segmented unit element MSB B1 binary weighted LSB B2 complexity proportional 2B1 1 B2 DNL compromise between the two Static performance Component matching Dynamic performance Time constants Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching Depending on the application reconstruction filter may be needed EECS 247 Lecture 18 Data Converters 2006 H K Page 10 What Next Analog Input ADC Converters Analog Preprocessing Need to build circuits that sample A D Conversion Need to build circuits for amplitude quantization D A Conversion Bits to Staircase Analog Post processing Reconstruction Filter DSP Anti Aliasing Filter Sampling Quantization 000 001 110 Analog Output EECS 247 Lecture 18 Data Converters 2006 H K Page 11 Analog to Digital Converters Two categories Nyquist rate ADCs fsigmax 0 5xfsampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max 12 14bits Oversampled ADCs fsigmax 0 5xfsampling Maximum possible signal bandwidth lower compared nyquist Maximum achievable resolution high 18 to 20bits EECS 247 Lecture 18 Data Converters 2006 H K Page 12 MOS Sampling Circuits EECS 247 Lecture 18 Data Converters 2006 H K Page 13 Ideal Sampling In an ideal world zero resistance sampling switches would close for the briefest instant to sample a continuous voltage vIN onto the capacitor C Output Dirac like pulses with amplitude equal to VIN at the time of sampling In practice not realizable EECS 247 Lecture 18 Data Converters 1 vIN vOUT S1 C 1 T 1 fS 2006 H K Page 14 Ideal T H Sampling 1 vIN vOUT S1 C 1 T 1 fS Vout tracks input when switch is closed Grab exact value of Vin when switch opens Track and Hold T H often called Sample Hold EECS 247 Lecture 18 Data Converters 2006 H K Page 15 Ideal T H Sampling time Hold T H signal Sampled Data Signal Track Continuous Time Clock Discrete Time Signal EECS 247 Lecture 18 Data Converters 2006 H K Page 16 Practical Sampling Issues 1 vIN vOUT M1 C Switch induced noise power due to M1 finite channel resistance Finite Rsw limited bandwidth finite acquisition time Rsw f Vin distortion Switch charge injection clock feedthrough Clock jitter EECS 247 Lecture 18 Data Converters 2006 H K Page 17 kT C Noise 1 vIN vOUT M1 C vIN 4kTR f R vOUT S1 C Switch resistance sampling capacitor form a low pass filter Noise associated with the switch resistance results in Total noise variance kT C the output see noise analysis in Lecture 1 In high resolution ADCs kT C noise often dominates overall minimum signal handling capability power dissipation considerations EECS 247 Lecture 18 Data Converters 2006 H K Page 18 Sampling Network kT C Noise For ADCs sampling capacitor size is usually chosen based on having thermal noise smaller or equal to quantization noise Assumption Nyquist rate ADC 2 12 Choose C such that thermal noise level is less or equal than Q noise For a Nyquist rate ADC Total quantization noise power k BT 2 C 12 2B 1 C 12k BT VFS C 12k BT 2 22 B VFS 2 EECS 247 Lecture 18 Data Converters 2006 H K Page 19 Sampling Network kT C Noise C 12k BT 22 B VFS 2 Required Cmin as a Function of ADC Resolution B Cmin VFS 1V Cmin VFS 0 5V 8 12 14 16 20 0 003 pF 0 8 pF 13 pF 206 pF 52 800 pF 0 012 pF 2 4 pF 52 pF 824 pF 211 200 pF The large area required for C limit highest achievable resolution for Nyquist rate ADCs Oversampling
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