EE247 Lecture 17 ADC Converters Sampling continued Sampling switch considerations Clock voltage boosters Sampling switch charge injection clock feedthrough Complementary switch Use of dummy device Bottom plate switching Track hold T H circuits T H combined with summing difference function T H circuit incorporating gain offset cancellation EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 1 Practical Sampling Summary So Far kT C noise C 12k BT 1 22 B VFS 2 vIN Finite Rsw limited bandwidth 0 72 R B f sC vOUT M1 C gsw f Vin distortion W Vin gON go 1 for go Cox VDD Vth V V L DD th Allowing long enough settling time reduce distortion due to sw non linear behavior EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 2 Signal Distortion Due to Sampling Switch Nonlinearity SFDR sensitive to sampling distortion improve linearity by Larger VDD VFS Higher sampling bandwidth Solutions Overdesign Larger switches Issue Increased switch charge injection Increased nonlinear S D junction cap Maximize VDD VFS Decreased dynamic range if VDD const Complementary switch Constant max VGS f Vin EECS 247 Lecture 17 10bit ADC Ts 20 VFS 1V VDD Vth 2V Data Converters ADC Design Sampling 2009 Page 3 Sampling Use of Complementary Switches 1 go 1B gon goT gon gop gop 1 1B Complementary n p switch advantages 9Increase in the overall conductance lower time constant 9Linearize the switch conductance for the range Vthp Vin Vdd Vthn EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 4 Complementary Switch Issues Supply Voltage Evolution Supply voltage has scaled down with technology scaling Threshold voltages do not scale accordingly Ref A Abo et al A 1 5 V 10 bit 14 3 MS s CMOS Pipeline Analog to Digital Converter JSSC May 1999 pp 599 EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 5 Complementary Switch Effect of Supply Voltage Scaling geffective gon 1 goT gon gop gop 1B 1 1B As supply voltage scales down input voltage range for constant go shrinks Complementary switch not effective when VDD becomes comparable to 2xVth EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 6 Boosted Constant VGS Sampling VGS const OFF ON Gate voltage VGS low Device off Beware of signal feedthrough due to parasitic capacitors EECS 247 Lecture 17 Increase gate overdrive voltage as much as possible keep VGS constant Switch overdrive voltage independent of signal level Error due to finite RON linear to 1st order Lower Ron lower time constant Data Converters ADC Design Sampling 2009 Page 7 Constant VGS Sampling voltage the switch input terminal EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 8 P N Constant VGS Sampling Circuit VDD 3V M2 M1 M3 M8 M6 M4 C1 P C3 C2 Vg P M5 PB Va M9 M12 M11 VS1 VP1 Vb Chold 1 5V 1MHz 100ns This Example All device sizes W L 10 0 35 Sampling switch C All capacitor size 1pF except for Chold Note Each critical switch requires a separate clock booster Ref A Abo et al A 1 5 V 10 bit 14 3 MS s CMOS Pipeline Analog to Digital Converter JSSC May 1999 pp 599 EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 9 Clock Voltage Doubler VDD 0 3V M1 0ff C2 PB 3V VthM2 6V VthM2 3V 0 3V Acquire charge C2 C1 PB 0 3V 0 0 3V 0 0 3V P P VP1 clock M2 off M1 Triode 0 3V VthM2 0 3V C1 VDD 3V M2 Saturation mode 0 3V a Start up EECS 247 Lecture 17 VP1 3V 0 b Next clock phase Data Converters ADC Design Sampling 2009 Page 10 Clock Voltage Doubler VDD 3V M1 0ff M2 M2 Triode 6V VthM2 3V VthM2 3V 3V 6V Acquires charge C2 C1 PB 0 3V 3V 0 P VP1 0 3V Both C1 C2 charged to VDD after 1 5 clock cycle Note that bottom plate of C1 C2 is either 0 or VDD while top plates are at VDD or 2VDD c Next clock phase EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 11 Clock Voltage Doubler 2VDD VDD 3V M2 M1 R1 P Boost R2 VDD C2 C1 PB P 0 VP1 Clock period 100ns EECS 247 Lecture 17 R1 R2 1GOhm dummy resistors added for simulation only Data Converters ADC Design Sampling 2009 Page 12 Constant VGS Sampler Low VDD 3V 2 VDD boosted clock VDD M3 Triode OFF Sampling switch M11 is OFF M4 C3 Device OFF M12 Triode VDD OFF M11 OFF VS1 1 5V 1MHz Input voltage source EECS 247 Lecture 17 Chold 1pF Data Converters ADC Design Sampling C3 charged to VDD 2009 Page 13 Constant VGS Sampler High C3 previously charged to VDD M8 VDD M8 M9 are on C3 across G S of M11 C3 1pF VS1 1 5V 1MHz EECS 247 Lecture 17 M11 on with constant VGS VDD M11 M9 Chold Mission accomplished Data Converters ADC Design Sampling 2009 Page 14 Constant VGS Sampling Input Switch VGate Chold Signal Input Signal EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 15 Constant VGS Sampling EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 16 Constant VGS Sampling IR During the time period Vin Vout VGS constant VDD Larger VGS Vth compared to no boost VGS cte and not a function of input voltage Significant linearity improvement EECS 247 Lecture 17 During the time period Vin Vout VGS VDD IR Larger VGS Vth compared to no boost VGS is a function of IR and hence input voltage Linearity improvement not as pronounced as for Vin Vout Data Converters ADC Design Sampling 2009 Page 17 Boosted Clock Sampling Complete Circuit Clock Multiplier M7 M13 for reliability Remaining issues VGS constant only for Vin Vout Nonlinearity due to Vth dependence of M11on bodysource voltage Switch Ref A Abo et al A 1 5 V 10 bit 14 3 MS s CMOS Pipeline Analog to Digital Converter JSSC May 1999 pp 599 EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 18 Boosted Clock Sampling Design Consideration Choice of value for C3 C3 too large large charging current large dynamic power VDD dissipation C3 too small Vgate Vs VDD C3 C3 Cx Loss of VGS due to low ratio of Cx C3 Cx includes CGS of M11 plus all other parasitics caps M8 C3 Cx M9 Vin M11 Chold Ref A Abo et al A 1 5 V 10 bit 14 3 MS s CMOS Pipeline Analog to Digital Converter JSSC May 1999 pp 599 EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 19 Advanced Clock Boosting Technique Ref M Waltari et al A self calibrated pipeline ADC with 200MHz IFsampling frontend ISSCC 2002 Dig Tech Papers pp 314 Sampling Switch Two floating voltages sources generated and connected to Gate and S D EECS 247 Lecture 17 Data Converters ADC Design Sampling 2009 Page 20 Advanced Clock Boosting Technique clk low Sampling Switch clk low Capacitors C1a C1b charged to VDD MS off Hold mode EECS …
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