EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 1EE247Lecture 17ADC Converters– Sampling (continued)• Sampling switch considerations– Clock voltage boosters• Sampling switch charge injection & clock feedthrough– Complementary switch– Use of dummy device– Bottom-plate switching– Track & hold • T/H circuits• T/H combined with summing/difference function• T/H circuit incorporating gain & offset cancellationEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 2Practical SamplingSummary So Far!22212BBFSCkTV≥()1 for inON o o ox DD thDD thWVgggCVVVVLμ⎛⎞=− = −⎜⎟−⎝⎠0.72sRBfC<<• kT/C noise• Finite RswÆ limited bandwidth• gsw= f (Vin) Æ distortion• Allowing long enough settling time Æ reduce distortion due to sw non-linear behaviorvINvOUTCM1φ1EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 3Signal Distortion Due to Sampling Switch Nonlinearity10bit ADC Ts/τ = 20VDD–Vth= 2V VFS= 1V• SFDR Æ sensitive to sampling distortion - improve linearity by:• Larger VDD /VFS• Higher sampling bandwidth• Solutions:• OverdesignÆ Larger switchesIssue: Æ Increased switchcharge injectionÆ Increased nonlinear S &D junction cap.• Maximize VDD/VFSÆDecreased dynamic range if VDDconst.• Complementary switch?• Constant & max. VGS≠ f(Vin)?EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 4SamplingUse of Complementary Switches φ1φ1Bφ1φ1BgongopgoT=gon+ gopgo•Complementary n & p switch advantages:9Increase in the overall conductance Æ lower time constant9Linearize the switch conductance for the range |Vthp|< Vin < Vdd -|Vthn|EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 5Complementary Switch IssuesSupply Voltage Evolution• Supply voltage has scaled down with technology scaling• Threshold voltages do not scale accordinglyRef: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599. EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 6Complementary SwitchEffect of Supply Voltage ScalinggongopgoT=gon+ gopgeffective•As supply voltage scales down input voltage range for constant goshrinksÆ Complementary switch not effective when VDDbecomes comparable to 2xVthφ1φ1Bφ1φ1BEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 7Boosted & Constant VGS SamplingVGS=const.OFFON• Increase gate overdrive voltage as much as possible + keep VGSconstant¾ Switch overdrive voltage independent of signal level¾ Error due to finite RONlinear (to 1st order)¾ Lower RonÆ lower time constant• Gate voltage VGS=low¾ Device off¾ Beware of signal feedthrough due to parasitic capacitorsEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 8Constant VGS Sampling(= voltage @ the switch input terminal)EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 9Constant VGS Sampling CircuitVP1100nsM12M8M9M6M11VS11.5V1MHzCholdPC1C2M1M2VDD=3VM3C3M5M4PThis Example: All device sizes:W/L=10μ/0.35μAll capacitor size: 1pF (except for Chold)Note: Each critical switch requires a separate clock boosterP_NVgVaVbSampling switch & CPBRef: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599. EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 10Clock Voltage DoublerC1C2M10ffM2Saturation modeVP1=clockPBVDD=0Æ3VPa) Start–up 0Æ3V0Æ3V0Æ00Æ3V0Æ(3V-VthM2)Acquire chargeC1C2M1Triode M2offVP1PBVDD=3VP3VÆ03VÆ03VÆ0Æ3V(3V-VthM2)Æ(6V-VthM2)b) Next clock phase 0Æ3VEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 11Clock Voltage DoublerC1C2M10ffM2VP1PBVDD=3VP0Æ3V0Æ3V3VÆ~6V3VÆ0c) Next clock phase (6V-VthM2)Æ(3V-VthM2)Æ~ 3VM2TriodeAcquires charge• Both C1 & C2 Æ charged to VDD after 1.5 clock cycle• Note that bottom plate of C1 & C2 is either 0 or VDD while top plates are at VDD or 2VDD EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 12Clock Voltage DoublerC1C2M1M2VP1Clock period: 100nsPBP_BoostVDD2VDD0VDD=3VR1 R2*R1 & R2=1GOhmÆ dummy resistors added for simulation onlyPEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 13Constant VGSSampler: Φ Low• Sampling switch M11 is OFF• C3 charged to ~VDDInput voltagesourceM3TriodeC3M12TriodeM4OFFVS11.5V1MHzChold1pF~ 2 VDD(boosted clock)VDDVDDOFFM11OFFDeviceOFFVDD=3VEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 14Constant VGSSampler: Φ High• C3 previously charged to VDD • M8 & M9 are on:C3 across G-S of M11• M11 on with constant VGS = VDD• Mission accomplished!?C31pFM8M9M11VS11.5V1MHzCholdVDDEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 15Constant VGS SamplingInput Switch VGateInput SignalChold SignalEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 16Constant VGS Sampling?EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 17• During the time period: Vin< VoutÆ VGS=constant=VDD– Larger VGS-Vthcompared to no boost–VGS=cte and not a function of input voltageÆ Significant linearity improvement• During the time period: Vin>Vout:Æ VGS= VDD-IR• Larger VGS-Vthcompared to no boost•VGSis a function of IR and hence input voltageÆ Linearity improvement not as pronounced as for Vin< VoutIRConstant VGSSampling?EECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 18Boosted Clock Sampling Complete CircuitRef: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599. Clock MultiplierSwitchM7 & M13 for reliabilityRemaining issues:-VGSconstant only for Vin<Vout-Nonlinearity due to Vth dependence of M11on body-source voltageEECS 247 Lecture 17: Data Converters- ADC Design, Sampling © 2009 Page 19Boosted Clock Sampling Design ConsiderationRef: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital
View Full Document
Unlocking...