EE247 Lecture 16 D A Converters continued Self calibration techniques Current copiers last lecture Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Clock jitter related non idealities Sampling switch bandwidth limitations Switch induced distortion Sampling switch conductance dependence on input voltage Clock voltage boosters EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 1 Data Converters DAC Design Intro to ADCs 2009 Page 2 Called Current Copier EECS 247 Lecture 16 16bit DAC 6 10 MSB DAC uses current copier technique I 2 Current Divider EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs I 2 I 2009 Page 3 Current Divider Inaccuracy due to Device Mismatch M1 M2 mismatch results in the two output currents not being exactly equal Id dI d Id dI d Id I 2 I 2 M1 M2 I 2 dId 2 M1 I 2 dId 2 M2 I d1 Id 2 I 2 I d1 Id 2 Id Ideal Current Divider d W L dVth W VGS Vth L 2 I Real Current Divider M1 M2 mismatched Problem Device mismatch could severely limit DAC accuracy Use of dynamic element matching next few pages EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 4 EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 5 Dynamic Element Matching Block Diagram Representation I 2 I1 CLKB I2 I1 I2 CLK CLK I2 I1 I 2 1 1 I 2 1 1 M1 M2 2 error 1 I I EECS 247 Lecture 16 I1 Data Converters DAC Design Intro to ADCs 2009 Page 6 Dynamic Element Matching During 2 During 1 I1 2 21 Io 1 1 I1 1 21 Io 1 1 I2 2 21 Io 1 1 I2 1 21 Io 1 1 Average of I2 T 1 fclk Io 2 Io 2 I1 I2 I 1 I2 2 I2 2 2 CLK 2 error 1 I 1 1 1 1 o 2 2 I o 2 EECS 247 Lecture 16 Note DAC frequency of operation fclk Data Converters DAC Design Intro to ADCs Note For optimum current division accuracy clock frequency is divided by two for each finer division Problem DAC frequency of operation drastically reduced fclk 4 fclk 2 Io 2009 Page 7 fclk fclk fclk fclk Note What if the same clock frequency is used EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 8 Dynamic Element Matching During 2 During 1 I1 1 12 I o 1 1 I 1 2 I o 1 1 1 2 I 3 1 12 I1 1 1 2 I o 1 1 1 2 1 4 I1 2 12 I o 1 1 I 2 2 I o 1 1 1 2 Io 4 I 3 2 12 I1 2 1 2 I 3 1 I 3 2 2 I o 1 1 1 2 1 1 1 2 4 2 I o 1 1 2 4 I2 I1 CLK E g 1 2 1 matching error is 1 2 0 01 EECS 247 Lecture 16 I4 2 error 2 14 I o 1 1 1 2 I3 I3 CLK Io 2 Io 4 Data Converters DAC Design Intro to ADCs 2 error 1 Io 2009 Page 9 Bipolar 12 bit DAC using dynamic element matching built in 1976 Element matching clock frequency 100kHz INL 0 25LSB EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 10 Example Stateof the Art current steering DAC Segmented 6bit unit element 8bit binary EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 11 EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 12 DAC In the Big Picture Analog Input Learned to build DACs Analog Preprocessing Convert the incoming digital signal to analog 000 001 110 DSP Some applications require filtering smoothing of DAC output reconstruction filter EECS 247 Lecture 16 Sampling Quantization A D Conversion DAC output staircase form Anti Aliasing Filter D A Conversion Bits to Staircase Analog Post processing Reconstruction Filter Analog Output Data Converters DAC Design Intro to ADCs 2009 Page 13 DAC Reconstruction Filter Need for and requirements depend on application DAC Input B fs 2 1 0 5 0 0 0 5 1 1 5 2 2 5 sinc 1 Tasks EECS 247 Lecture 16 DAC Output x 10 0 5 0 Correct for sinc droop Remove aliases stair case approximation 3 6 0 0 5 1 1 5 2 2 5 1 3 6 x 10 0 5 0 0 0 5 1 1 5 2 2 5 Normalized Frequency Data Converters DAC Design Intro to ADCs 3 f fs 2009 Page 14 Reconstruction Filter Options Reconstruction Filters Digital Filter DAC SC Filter CT Filter Reconstruction filter options Continuous time filter only CT SC filter SC filter possible only in combination with oversampling signal bandwidth B fs 2 Digital filter Band limits the input signal prevent aliasing Could also provide high frequency pre emphasis to compensate inband sinx x amplitude droop associated with the inherent DAC S H function EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 15 DAC Reconstruction Filter Example Voice Band CODEC Receive Path Receive Output fs 8kHz fs 8kHz fs 128kHz fs 128kHz Reconstruction Filter sinx x Compensator GSR fs 128kHz Note fsigmax 3 4kHz fsDAC 8kHz sin fsigmax x Ts fsigmax xTs 2 75 dB droop due to DAC sinx x shape Ref D Senderowicz et al A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip IEEE Journal of Solid State Circuits Vol SC 17 No 6 pp 1014 1023 Dec 1982 EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 16 Summary D A Converter D A architecture Unit element complexity proportional to 2B excellent DNL Binary weighted complexity proportional to B poor DNL Segmented unit element MSB B1 binary weighted LSB B2 Complexity proportional 2B1 1 B2 DNL compromise between the two Static performance Component matching Dynamic performance Time constants Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching Depending on the application reconstruction filter may be needed EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 17 What Next Analog Input ADC Converters Analog Preprocessing Need to build circuits that sample A D Conversion Need to build circuits for amplitude quantization D A Conversion Bits to Staircase Analog Post processing Reconstruction Filter DSP Anti Aliasing Filter Sampling Quantization 000 001 110 Analog Output EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 18 Analog to Digital Converters Two categories Nyquist rate ADCs fsigmax 0 5xfsampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max 12 14bits Oversampled ADCs fsigmax 0 5xfsampling Maximum achievable signal bandwidth significantly lower compared to nyquist Maximum achievable resolution high 18 to 20bits EECS 247 Lecture 16 Data Converters DAC Design Intro to ADCs 2009 Page 19 MOS Sampling Circuits EECS 247 Lecture 16 Data Converters DAC …
View Full Document
Unlocking...