EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 1EE247Lecture 16• D/A Converters (continued)– Self calibration techniques• Current copiers (last lecture)• Dynamic element matching– DAC reconstruction filter• ADC Converters– Sampling• Sampling switch considerations– Thermal noise due to switch resistance – Clock jitter related non-idealities– Sampling switch bandwidth limitations– Switch induced distortion• Sampling switch conductance dependence on input voltage• Clock voltage boostersEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 2Called: Current CopierEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 3II/2I/2Current Divider16bit DAC (6+10) - MSB DAC uses current copier techniqueEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 4II/2I/2Ideal Current DividerCurrent Divider Inaccuracy due to Device MismatchII/2+dId /2Real Current Divider M1& M2 mismatchedI/2-dId /2M1M2M1M2ÆProblem: Device mismatch could severely limit DAC accuracyÆ Use of dynamic element matching (next few pages)M1 & M2 mismatch results in the two output currents not being exactly equal:d1 d2ddd1d2ddWLdthWLdGSthIII2dI I IIIddI 2dVIVV+=−==Δ⎡⎤⎛⎞=×+⎢⎥⎜⎟−⎝⎠⎣⎦EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 5EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 6/ 2 error Δ1II/2(1-Δ1)M1M2I/2(1+Δ1)I2`CLKCLKCLKBÆI1`I2I1ÆI2`I1`I2I1Dynamic Element MatchingBlock Diagram RepresentationIEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 7Dynamic Element Matching()()(1) (2)22211ooIII211I22I2+=−Δ + +Δ=≈()()(1)1o112(1)1o122II1II1=+Δ=−Δ/ 2 error Δ1I1During Φ1During Φ2I2CLKIoIo/2Io/2()()(2)1o112(2)1o122II1II1=−Δ=+ΔAverage of I2 :Note: DAC frequency of operation << fclkT=1/fclkEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 8Note: For optimum current division accuracy Æ clock frequency is divided by two for each finer divisionProblem: DAC frequency of operation drastically reducedNote: What if the same clock frequency is used?fclk/2fclk/4fclkfclkfclkfclkEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 9Dynamic Element Matching()()()()()21412)1(121)1(3121)1(2121)1(111111Δ+Δ+=Δ+=Δ−=Δ+=oooIIIIIII()()()()()21412)2(121)2(3121)2(2121)2(111111Δ−Δ−=Δ−=Δ+=Δ−=oooIIIIIIIDuring Φ1During Φ2()()()()()212121)2(3)1(33142111142ΔΔ+=Δ−Δ−+Δ+Δ+=+=ooIIIIIE.g. Δ1= Δ2= 1% Æ matching error is (1%)2= 0.01%/ 2 error Δ1I1I2CLKIoIo/2/ 2 error Δ2I3I4CLKIo/4Io/4EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 10• Bipolar 12-bit DAC using dynamic element matching built in 1976• Element matching clock frequency 100kHz• INL <0.25LSB!EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 11Example: State-of-the-Art current steering DACSegmented:6bit unit-element 8bit binaryEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 12EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 13DAC In the Big Picture• Learned to build DACs– Convert the incoming digital signal to analog• DAC output Æstaircase form• Some applications require filtering (smoothing) of DAC output Æ reconstruction filterAnalog Post processingD/AConversionDSPA/D ConversionAnalog PreprocessingAnalog InputAnalog Output000...001...110Anti-AliasingFilterSampling+Quantization"Bits to Staircase"Reconstruction FilterEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 14DAC Reconstruction Filter• Need for and requirements depend on application• Tasks:– Correct for sinc droop– Remove “aliases”(stair-case approximation)B fs/20 0.5 1 1.5 2 2.5 3x 10600.51DAC Input0 0.5 1 1.5 2 2.5 3x 10600.51sinc0 0.5 1 1.5 2 2.5 300.51DAC OutputNormalized Frequencyf/fsEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 15Reconstruction Filter Options• Reconstruction filter options:– Continuous-time filter only– CT + SC filter• SC filter possible only in combination with oversampling (signalbandwidth B << fs/2)• Digital filter– Band limits the input signal Æ prevent aliasing– Could also provide high-frequency pre-emphasis to compensate in-band sinx/x amplitude droop associated with the inherent DAC S/H functionDigitalFilterDACSCFilterCTFilterReconstruction FiltersEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 16DAC Reconstruction Filter Example: Voice-Band CODEC Receive PathRef: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,”IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.Note: fsigmax = 3.4kHzfsDAC = 8kHzÆsin(π fsigmax x Ts )/(π fsigmax xTs )= -2.75 dB droop due to DAC sinx/x shapeReceive Outputfs= 8kHzfs= 128kHzfs= 8kHzfs= 128kHzfs= 128kHzGSRReconstruction Filter& sinx/x CompensatorEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 17SummaryD/A Converter • D/A architecture – Unit element – complexity proportional to 2B- excellent DNL – Binary weighted- complexity proportional to B- poor DNL– Segmented- unit element MSB(B1)+ binary weighted LSB(B2)Æ Complexity proportional ((2B1-1) + B2) -DNL compromise between the two• Static performance– Component matching• Dynamic performance– Time constants, Glitches• DAC improvement techniques – Symmetrical switching rather than sequential switching– Current source self calibration– Dynamic element matching• Depending on the application, reconstruction filter may be neededEECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs © 2009 Page 18What Next?• ADC Converters:– Need to build circuits that "sample“– Need to build circuits for amplitude quantizationAnalog Post processingD/AConversionDSPA/D ConversionAnalog PreprocessingAnalog InputAnalog
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