EE247 Lecture 19 ADC Converters Sampling continued Clock boosters continued Sampling switch charge injection clock feedthrough Complementary switch Use of dummy device Bottom plate switching Track hold circuits T H circuit incorporating gain offset cancellation Electro Static Discharge ESD protection EECS 247 Lecture 19 Data Converters 2006 H K Page 1 Summary Last Lecture DAC Converters continued DAC reconstruction filter ADC Converters Sampling Sampling network thermal noise Acquisition bandwidth limitations For example 1 accuracy Ts 2 5RC Sampling switch induced distortion Sampling switch conductance dependence on input voltage Complementary switch Clock boosters EECS 247 Lecture 19 Data Converters 2006 H K Page 2 Boosted Clock Sampling Complete Circuit Clock Multiplier M7 M13 for reliability Remaining issues VGS constant only for Vin Vout Nonlinearity due to Vth dependence of M11on bodysource voltage Switch Ref A Abo et al A 1 5 V 10 bit 14 3 MS s CMOS Pipeline Analog to Digital Converter JSSC May 1999 pp 599 EECS 247 Lecture 19 Data Converters 2006 H K Page 3 Advanced Clock Boosting Technique Ref M Waltari et al A self calibrated pipeline ADC with 200MHz IFsampling frontend ISSCC 2002 Dig Tech Papers pp 314 Sampling Switch EECS 247 Lecture 19 Data Converters 2006 H K Page 4 Advanced Clock Boosting Technique clk low Sampling Switch clk low Capacitors C1a C1b charged to VDD MS off Hold mode EECS 247 Lecture 19 Data Converters 2006 H K Page 5 Advanced Clock Boosting Technique clk high clk high Sampling Switch Top plate of C1a C1b connected to gate of sampling switch Bottom plate of C1a connected to VIN Bottom plate of C1b connected to VOUT VGS VGD of MS both VDD ac signal on G of MS average of VIN VOUT EECS 247 Lecture 19 Data Converters 2006 H K Page 6 Advanced Clock Boosting Technique Ref M Waltari et al A self calibrated pipeline ADC with 200MHz IFsampling frontend ISSCC 2002 Dig Tech Papers pp 314 Sampling Switch Gate tracks average of input and output reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect technology used allows connecting bulk to S Reported measured SFDR 76 5dB at fin 200MHz EECS 247 Lecture 19 Data Converters 2006 H K Page 7 Constant Conductance Switch Ref H Pan et al A 3 3 V 12 b 50 MS s A D converter in 0 6um CMOS with over 80 dB SFDR IEEE J Solid State Circuits pp 1769 1780 Dec 2000 EECS 247 Lecture 19 Data Converters 2006 H K Page 8 Constant Conductance Switch OFF Ref H Pan et al A 3 3 V 12 b 50 MS s A D converter in 0 6um CMOS with over 80 dB SFDR IEEE J Solid State Circuits pp 1769 1780 Dec 2000 EECS 247 Lecture 19 Data Converters 2006 H K Page 9 Constant Conductance Switch M2 Constant current constant gds M1 replica of M2 same VGS as M2 M1 also constant gds ON Note Authors report requirement of 280MHz GBW for the opamp for 12bit 50Ms s ADC Also opamp common mode compliance for full input range Ref H Pan et al A 3 3 V 12 b 50 MS s A D converter in 0 6um CMOS with over 80 dB SFDR IEEE J Solid State Circuits pp 1769 1780 Dec 2000 EECS 247 Lecture 19 Data Converters 2006 H K Page 10 Switch Off Mode Feedthrough Cancellation Ref M Waltari et al A self calibrated pipeline ADC with 200MHz IF sampling frontend ISSCC 2002 Dig Techn Papers pp 314 EECS 247 Lecture 19 Data Converters 2006 H K Page 11 Practical Sampling 1 Vi Vo M1 C Rsw f Vi distortion Switch charge injection clock feedthrough EECS 247 Lecture 19 Data Converters 2006 H K Page 12 Sampling Switch Charge Injection Clock Feedthrough Switching from Track to Hold VG VG VH Vi Vth Vi Vi VL M1 Cs t VO VO V Vi t toff First assume Vi is a DC voltage When switch turns off offset voltage induced on Cs Why EECS 247 Lecture 19 Data Converters 2006 H K Page 13 Sampling Switch Charge Injection Distributed channel resistance gate junction capacitances G Cov Cov MOS xtor operating in triode region Cross section view LD L S D CHOLD Cjdb Cjsb B Channel distributed RC network formed between G S and D Channel to substrate junction capacitance distributed voltage dependant Drain Source junction capacitors to substrate voltage dependant Over lap capacitance Cov LDxWxCox associated with G S G D overlap EECS 247 Lecture 19 Data Converters 2006 H K Page 14 Switch Charge Injection Slow Clock VH VG Device still conducting Vi Vth Vi VL t t toff Slow clock clock fall time device speed During the period t to toff current in channel discharges channel charge into low impedance signal source Only source of error Clock feedthrough from Cov to Cs EECS 247 Lecture 19 Data Converters 2006 H K Page 15 Switch Clock Feedthrough Slow Clock VG VG VH Cov Vi Vth Vi D Cs VL t VO V Cov Cov Cs Vi Vth VL Co v Vi Vth VL Cs Vo Vi V C C C Vo Vi o v Vi Vth VL Vi 1 o v o v Vth VL Cs Cs Cs Vo Vi 1 Vos wh e re V Vi Cov Cs Vo s Cov Cs t toff t Vth VL EECS 247 Lecture 19 Data Converters 2006 H K Page 16 Switch Charge Injection Clock Feedthrough Slow Clock Example VG 10 0 18 Vi M1 VG VO VH Cs 1pF Vi Vi Vth VL t VO C ov 0 1 fF Cox 9 fF 2 Vth 0 4V VL 0 V Vi 10 x0 1 fF 1 Cs 1pF Allowing 1 2LSB ADC r e solution 9bit Cov Vos Cov Cs t toff Vth VL 0 4mV t EECS 247 Lecture 19 Data Converters 2006 H K Page 17 Switch Charge Injection Clock Feedthrough Fast Clock Qch VG Vi nQch n m 1 VG M1 mQch VH Vi Vth VO Vi Cs 1pF VL t VO V Vi toff t Sudden gate voltage drop no gate voltage to establish current in channel channel charge has no choice but to escape out towards S D EECS 247 Lecture 19 Data Converters 2006 H K Page 18 Switch Charge Injection Clock Feedthrough Fast Clock VG Clock Fall Time Device Speed VH Vo Co v Co v Cs 1 VH VL 2 Vi Vth Q ch Cs Vi 1 WCox L VH Vi Vth Co v Co v Cs VH VL 2 Cs VL Co v Cs V Vi 1 WCo x L w he r e 2 Cs Vo s t VO Vo Vi Vo Vi 1 Vo s 1 WCo x L VH Vth VH VL 2 Cs toff t For simplicity it is assumed channel charge divided equally between S D Source of error channel charge transfer clock feedthrough via Cov to Cs EECS 247 Lecture 19 Data Converters 2006 H K Page 19 Switch Charge Injection Clock Feedthrough Fast Clock Example VG VG 10 0 18 Vi VH Vi Vth VO M1 VIN Cs …
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