EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 1EE247Lecture 19ADC Converters• Sampling (continued)– Clock boosters (continued)– Sampling switch charge injection & clock feedthrough• Complementary switch• Use of dummy device• Bottom-plate switching– Track & hold circuits– T/H circuit incorporating gain & offset cancellation•Electro-Static Discharge (ESD) protectionEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 2Summary Last Lecture• DAC Converters (continued)– DAC reconstruction filter• ADC Converters–Sampling• Sampling network thermal noise• Acquisition bandwidth limitations– For example 1% accuracyÆ Ts /2>5RC• Sampling switch induced distortion– Sampling switch conductance dependence on input voltage– Complementary switch– Clock boostersEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 3Boosted Clock Sampling Complete CircuitRef: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599. Clock MultiplierSwitchM7 & M13 for reliabilityRemaining issues:-VGSconstant only for Vin<Vout-Nonlinearity due to Vth dependence of M11on body-source voltage EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 4Advanced Clock Boosting TechniqueRef: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314Sampling SwitchEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 5Advanced Clock Boosting Technique•clkÆ low– Capacitors C1a & C1b Æ charged to VDD–MS Æ off– Hold modeSampling SwitchclkÆ lowEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 6Advanced Clock Boosting TechniqueSampling Switch•clkÆ high– Top plate of C1a & C1b connected to gate of sampling switch– Bottom plate of C1a connected to VIN– Bottom plate of C1b connected to VOUT– VGS & VGD of MS both @ VDD & ac signal on G of MS Æ average of VIN& VOUTclkÆ highEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 7Advanced Clock Boosting Technique• Gate tracks average of input and output, reduces effect of I·R drop at high frequencies• Bulk also tracks signal ⇒ reduced body effect (technology used allows connecting bulk to S)• Reported measured SFDR = 76.5dB at fin=200MHzRef: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314Sampling SwitchEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 8Constant Conductance SwitchRef: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 9Constant Conductance SwitchRef: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000OFFEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 10Constant Conductance SwitchRef: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000ONM2Æ Constant currentÆ constant gdsM1Æ replica of M2 & same VGSas M2Æ M1 alsoconstant gds• Note: Authors report requirement of 280MHz GBW for the opamp for 12bit 50Ms/s ADC• Also, opamp common-mode compliance for full input rangeEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 11Switch Off-Mode Feedthrough CancellationRef: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 12Practical SamplingVoCM1φ1•Rsw= f(Vi) Æ distortion• Switch charge injection & clock feedthroughViEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 13Sampling Switch Charge Injection & Clock FeedthroughSwitching from Track to HoldViVOCsM1VG• First assume Viis a DC voltage• When switch turns off Æ offset voltage induced on Cs•Why?VGtVHViVLVi +VthVOVitoffΔVtEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 14SamplingSwitch Charge Injection• Channel Æ distributed RC network formed between G,S, and D• Channel to substrate junction capacitance Æ distributed & voltage dependant• Drain/Source junction capacitors to substrate Æ voltage dependant• Over-lap capacitance Cov = LDxWxCox’associated with G-S & G-D overlapMOS xtor operating in triode regionCross section viewDistributed channel resistance & gate & junction capacitancesSGDBLDLCovCovCjdbCjsbCHOLDEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 15Switch Charge Injection Slow Clock•Slow clockÆ clock fall time >> device speed Æ During the period (t- to toff) current in channel discharges channel charge into low impedance signal source• Only source of error Æ Clock feedthrough from Cov to CsVGtVHViVLVi +Vthtofft-Device still conductingEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 16Switch Clock Feedthrough Slow ClockVGtVHViVLVi +VthVOVitoffΔVtDCovVG()()() ()()()ovithLov sovithLsoiov ov ovoi ithL i thLsssoi osov ovos th LssCVVVVCCCVV VCVV VCCCVV VVV V1 VVCCCVV1 VCCwhere ; V V VCCεεΔ=− + −+≈− + −=+Δ⎛⎞=− + − = − − −⎜⎟⎜⎟⎝⎠=++=− =− −t-CsEECS 247 Lecture 19: Data Converters © 2006 H.K. Page 17Switch Charge Injection & Clock Feedthrough Slow Clock- Example()'2ovox th Lovsovos th LsC0.1fF/C9fF/V0.4VV0C10x0.1fF/.1%C1pFAllowing 1/2LSB ADCresolution ~9bitCVVV0.4mVCμμμμεε=====− =− =−=→ <=− − =−VGtVHViVLVi +VthVOVitoffΔVtViVOCs=1pFM1VG10μ/0.18μt-EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 18Switch Charge Injection & Clock Feedthrough Fast ClockVGtVHViVLVi +VthVOVitoffΔVtViVOCs=1pFM1VG• Sudden gate voltage drop Æ no gate voltage to establish current in channel Æ channel charge has no choice but to escape out towards S & DQchmQchnQchn+m=1EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 19()()()()()()()ov choHLov s soxHithovHLov s soioi osoxsov ox H thos H LssC1QVVVCC 2CWC L V V VC1VVCC 2 CVVVV1 V1WCLwhere2CC1WCLVVVVVC2CεεΔ=− − − ×+−−≈− − − ×+=−=++=×−=− − − ו For simplicity it is assumed channel charge divided equally between S & D • Source of error Æ channel charge transfer + clock feedthrough via Covto Cs VGtVHViVLVi +VthVOVitoffΔVtSwitch Charge Injection & Clock FeedthroughFast ClockClock Fall-Time << Device Speed:EECS 247 Lecture 19: Data
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