EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 1EE247Lecture 18ADC Converters– Sampling (continued)• Sampling switch charge injection & clock feedthrough– Complementary switch– Use of dummy device– Bottom-plate switching– Track & hold • T/H circuits• T/H combined with summing/difference function• T/H circuit incorporating gain & offset cancellation• T/H aperture uncertaintyEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 2Practical SamplingIssuesvINvOUTCM1φ1• Switch induced noise due to M1 finite channel resistance• Clock jitter• Finite RswÆ limited bandwidth Æ finite acquisition time• Rsw= f(Vin) Æ distortion• Switch charge injection & clock feedthroughEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 3Sampling Switch Charge Injection & Clock FeedthroughSwitching from Track to HoldViVOCsM1VG• First assume Viis a DC voltage• When switch turns off Æ offset voltage induced on Cs•Why?VGtVHViVLVi +VthVOVitoffΔVtEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 4SamplingSwitch Charge Injection• Channel Æ distributed RC network formed between G,S, and D• Channel to substrate junction capacitance Æ distributed & voltage dependant• Drain/Source junction capacitors to substrate Æ voltage dependant• Over-lap capacitance Cov = LDxWxCox’associated with G-S & G-D overlapMOS xtor operating in triode regionCross section viewDistributed channel resistance & gate & junction capacitancesSGDBLDLCovCovCjdbCjsbCHOLDEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 5Switch Charge Injection Slow Clock•Slow clockÆ clock fall time >> device speed Æ During the period (t- to toff) current in channel discharges channel charge into low impedance signal source• Only source of error Æ Clock feedthrough from Cov to CsVGtVHViVLVi +Vthtofft-Device still conductingEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 6Switch Clock Feedthrough Slow ClockVGtVHViVLVi +VthVOVitoffΔVtDCovVGt-Cs()()() ()()()ovithLov sovithLsoiov ov ovoi ithL i thLsssoi osov ovos th LssCVVVVCCCVV VCVV VCCCVV VVV V1 VVCCCVV1 VCCwhere ; V V VCCεεΔ=− + −+≈− + −=+Δ⎛⎞=− + − = − − −⎜⎟⎜⎟⎝⎠=++=− =− −EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 7Switch Charge Injection & Clock Feedthrough Slow Clock- ExampleVGtVHViVLVi +VthVOVitoffΔVtViVOCs=1pFM1VG10μ/0.18μt-()'2ovox th Lovsovos th LsC 0.1fF / C 9fF / V 0.4V V 0C10x0.1fF/.1%C1pFAllowing 1/ 2LSB ADCresolution ~9bitCVVV0.4mVCμμμμεε=====− =− =−=→ <=− − =−EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 8Switch Charge Injection & Clock Feedthrough Fast ClockVGtVHViVLVi +VthVOVitoffΔVtViVOCs=1pFM1VG• Sudden gate voltage drop Æ no gate voltage to establish current in channel Æ channel charge has no choice but to escape out towards S & DQchmQchnQchn+m=1EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 9• For simplicity it is assumed channel charge divided equally between S & D • Source of error Æ channel charge transfer + clock feedthrough via Covto Cs VGtVHViVLVi +VthVOVitoffΔVtSwitch Charge Injection & Clock FeedthroughFast ClockClock Fall-Time << Device Speed:()()()()()()()ov choHLov s sox H i thovHLov s soi osoxsox H thovos H LssC1QVVVCC 2CWC L V V VC1VVCC 2 CVV1 V1WCLwhere2CWC L V VC1VVVC2CεεΔ=− − − ×+−−≈− − − ×+=++=×−=− − − ×EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 10Switch Charge Injection & Clock FeedthroughFast Clock- ExampleViVOCs=1pFM1VG10μ/0.18μ()()ov ox th DD L22oxsox H thovos H LssfF fFC 0.1 , C 9 ,V 0.4V,V 1.8V,V 0WLC 10 x0.18 x9fF /1/2 1.6% ~5 bitC1pFWC L V VC1V V V 1.8mV 14.6mV 16.4mVC2Cμμμμ με======= =→−−=− − − × =− − =−VGtVHViVLVi +VthVOVitoffΔVtEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 11Switch Charge Injection & Clock FeedthroughExample-SummaryError function of:Æ Clock fall time Æ Input voltage level Æ Source impedance Æ Sampling capacitance size Æ Switch size³Clock fall/rise should be controlled not to be faster (sharper) than necessaryClock fall timeεVOSClock fall time1.6%.1%16mV0.4mVEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 12Switch Charge InjectionError Reduction• How do we reduce the error? Æ Reduce switch size to reduce channel charge? Reducing switch size increases τ Æ increased distortionÆ not a viable solution Smallτ and small ΔV Æ use minimum chanel length (mandated by technology) For a given technology τ x ΔV ~ constant()()()()chosssON sox GS thox GS thsos oxHith21QV2CCTR C (note: kW2CVVLConsider the figure of merit (FOM):WCVV1CLFOM 2VC WCLVVVFOM L)μμμτττΔ=− ↓== ↑ =−−=≈ ×Δ−−→∝××EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 13Sampling Switch Charge Injection & Clock FeedthroughSummary• Extra charge injected onto sampling capacitor @ switch device turn-off–Channel charge injection–Clock feedthrough to Csvia Cov• Issues due to charge injection & clock feedthrough:–DC offset induced on hold C–Input dependant error voltage Æ distortion• Solutions:–Slowing down clock edges as much as possible–Complementary switch?–Addition of dummy switches?–Bottom-plate sampling?EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 14Switch Charge Injection & Clock FeedthroughComplementary Switch• In slow clock case if area of n & p devices widths are equal (Wn=Wp)Æeffect of overlap capacitor for n & p devices to first order cancel (cancellation accuracy depends on matching of n & p width and overlap length LD)• Since in CMOS technologies μn~2.5μp choice of Wn=Wpnot optimal from linearity perspective (Wp>Wnpreferable)φ1φ1Bφ1φ1BVGtVHViVLφ1φ1BEECS 247- Lecture 18 Nyquist Rate ADCs-Sampling Networks © 2008 H.K. Page 15Switch Charge Injection
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