EE247 Lecture 18 ADC Converters Sampling continued Sampling switch charge injection clock feedthrough Complementary switch Use of dummy device Bottom plate switching Track hold T H circuits T H combined with summing difference function T H circuit incorporating gain offset cancellation T H aperture uncertainty EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 1 Practical Sampling Issues 1 vIN vOUT M1 C Switch induced noise due to M1 finite channel resistance Clock jitter Finite Rsw limited bandwidth finite acquisition time Rsw f Vin distortion Switch charge injection clock feedthrough EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 2 Sampling Switch Charge Injection Clock Feedthrough Switching from Track to Hold VG VG VH Vi Vth Vi Vi VL M1 Cs t VO VO V Vi t toff First assume Vi is a DC voltage When switch turns off offset voltage induced on Cs Why EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 3 Sampling Switch Charge Injection Distributed channel resistance gate junction capacitances G Cov Cov MOS xtor operating in triode region Cross section view LD L S D CHOLD Cjdb Cjsb B Channel distributed RC network formed between G S and D Channel to substrate junction capacitance distributed voltage dependant Drain Source junction capacitors to substrate voltage dependant Over lap capacitance Cov LDxWxCox associated with G S G D overlap EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 4 Switch Charge Injection Slow Clock VH VG Device still conducting Vi Vth Vi VL t t toff Slow clock clock fall time device speed During the period t to toff current in channel discharges channel charge into low impedance signal source Only source of error Clock feedthrough from Cov to Cs EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 5 Switch Clock Feedthrough Slow Clock VG VG VH Cov Vi Vth Vi D V Cov Cov Cov Cs Vi Vt h VL Cs VL Vi Vt h VL Vi Cs Vo Vi V C C C Vo Vi ov Vi Vt h VL Vi 1 ov ov Vt h VL Cs Cs Cs Vo Vi 1 Vos where Cov Cs Vo s EECS 247 Lecture 18 Cov Cs t VO V t toff t Vt h VL Nyquist Rate ADCs Sampling Networks 2008 H K Page 6 Switch Charge Injection Clock Feedthrough Slow Clock Example VG 10 0 18 Vi VG VO VH Cs 1pF Vi M1 Vi Vth VL C o v 0 1 f F Co x 9 f F 2 Vt h 0 4V V VL 0 V i 1 0 x0 1 f F 1 Cs 1p F Al l o w i n g 1 2L S B ADC reso l u t i o n 9b i t t VO Cov Vo s Co v Cs t toff t Vt h VL 0 4mV EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 7 Switch Charge Injection Clock Feedthrough Fast Clock Qch VG Vi nQch n m 1 VG M1 mQch VH Vi Vth VO Vi Cs 1pF VL t VO V Vi toff t Sudden gate voltage drop no gate voltage to establish current in channel channel charge has no choice but to escape out towards S D EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 8 Switch Charge Injection Clock Feedthrough Fast Clock VG Clock Fall Time Device Speed VH Cov Vo Cov Cs Cov VH VL VH VL 1 2 Qch Cs 1 WCo x L VH Vi Vt h 2 Cs Cov Cs Vo Vi 1 Vos 1 WCox L where 2 Cs Cov 1 WC L V V Vos VH VL ox H t h Cs 2 Cs Vi Vth Vi VL t VO V Vi toff t For simplicity it is assumed channel charge divided equally between S D Source of error channel charge transfer clock feedthrough via Cov to Cs EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 9 Switch Charge Injection Clock Feedthrough Fast Clock Example VG VG 10 0 18 Vi VH Vi Vth VO M1 Vi Cs 1pF VL t VO V Vi Co v 0 1 1 2 fF Co x 9 WL Co x Co v Cs Vt h 0 4V VDD 1 8V VL 0 1 0 x0 18 x9 fF 2 Cs Vos fF 2 VH VL EECS 247 Lecture 18 1 6 5 bi t 1p F toff t 1 WCox L VH Vt h 1 8mV 14 6mV 16 4mV 2 Cs Nyquist Rate ADCs Sampling Networks 2008 H K Page 10 Switch Charge Injection Clock Feedthrough Example Summary VOS 1 6 16mV 1 0 4mV Clock fall time Clock fall time Error function of Clock fall time Input voltage level Source impedance Sampling capacitance size Switch size Clock fall rise should be controlled not to be faster sharper than necessary EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 11 Switch Charge Injection Error Reduction How do we reduce the error Reduce switch size to reduce channel charge 1 Qch Vo 2 Cs Cs T RON Cs n o t e s k W 2 Cox VGS Vth L C o n s i d er t he f i g u r e o f mer i t FO M W Cox VGS Vth 1 Cs L 2 FOM Cs WCox L VH Vi Vt h Vo F OM L2 Reducing switch size increases increased distortion not a viable solution Small and small V use minimum chanel length mandated by technology For a given technology x V constant EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 12 Sampling Switch Charge Injection Clock Feedthrough Summary Extra charge injected onto sampling capacitor switch device turn off Channel charge injection Clock feedthrough to Cs via Cov Issues due to charge injection clock feedthrough DC offset induced on hold C Input dependant error voltage distortion Solutions Slowing down clock edges as much as possible Complementary switch Addition of dummy switches Bottom plate sampling EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 13 Switch Charge Injection Clock Feedthrough Complementary Switch 1 VG VH 1B 1 1B 1 1B Vi VL t In slow clock case if area of n p devices widths are equal Wn Wp effect of overlap capacitor for n p devices to first order cancel cancellation accuracy depends on matching of n p width and overlap length LD Since in CMOS technologies n 2 5 p choice of Wn Wp not optimal from linearity perspective Wp Wn preferable EECS 247 Lecture 18 Nyquist Rate ADCs Sampling Networks 2008 H K Page 14 Switch Charge Injection Complementary Switch Fast Clock Qc h n WnCo x Ln VH Vi Vth n VG VH Qc h p WpCo x Lp Vi VL Vth p Qc h p 1 Q Vo c h n 2 Cs Cs Vi VL t Vo Vi 1 Vo s 1 1 WnCo x Ln …
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