6 375 Complex Digital System Spring 2006 Do we need more chips ASICs ASIC Application Specific IC Lecturer TAs Assistant February 8 2006 Some exciting possibilities based on research CSAIL Arvind Chris Batten Mike Pellauer Sally Lee http csg csail mit edu 6 375 L01 1 Content distribution and customer service February 8 2006 http csg csail mit edu 6 375 Source Computer Science and Artificial Intelligence Laboratory at MIT CSAIL L01 2 Ubiquitous behind the scenes computing Interactive lifelike avatars as actors news anchors and customer service representatives February 8 2006 http csg csail mit edu 6 375 Computer interfaces woven tightly into the environment L01 3 February 8 2006 Source Computer Science and Artificial Intelligence Laboratory at MIT CSAIL http csg csail mit edu 6 375 L01 4 Current Cellphone Architecture What s required WLAN WLAN RF RF ICs with dramatically higher performance optimized for applications Application Processing WLAN RF WCDMA GSM RF Two chips each with an ARM general purpose processor GPP and a DSP Comms Processing TI OMAP 2420 M O C and at a size and power to deliver mobility cost to address mass consumer markets Source http www intel com technology silicon mooreslaw index htm February 8 2006 http csg csail mit edu 6 375 L01 5 Chip design has become too risky a business 10M for a 10M gate ASIC 1M per re spin in case of an error does not include the redesign costs which can be substantial February 8 2006 Fewer new chip starts every year Looking for alternatives e g FPGA s http csg csail mit edu 6 375 Constants 10 30 person design team size 18 month design schedule Design flow unchanged for 10 years Conservative design No time for exploration Educated guess code Gates are free mentality gates ns Pipeline Which is best Memory Util Static 8 898 3 60 63 5 Linear 15 910 4 70 99 9 Circular 8 170 3 67 99 9 Static 2 2 391 3 32 63 5 ICCAD 04 18 months to design but only an eight month selling opportunity in the market 2000 1M logic gates 2005 10M logic gates 2010 100M logic gates Designer must take shortcuts LPM LPM Pipeline Area example Speed Ever increasing costs and design team sizes L01 6 Designer s Dilemma Microprocessors 100M gates 1000M gates ASICs 5M to 10M gates 50M to 100M gates X http csg csail mit edu 6 375 ASIC Complexity Ever increasing size and complexity February 8 2006 E PL What happens when a designer must implement a 1M gate block Sub optimal implementations Alternatives L01 7 February 8 2006 http csg csail mit edu 6 375 L01 8 One prevailing viewpoint A sea of general purpose processors Advantages Easier to scale hardware design as complexity is contained within processors Easy to program and debug complex applications Another popular platform vision Field Programmable Gate Arrays Advantages IBM Sony Cell Processor Dramatically reduce the cost of errors Remove the reticle costs from each design Disadvantages as compared to an ASIC Disadvantages as compared to an ASIC Power 100 1000X worse Performance up to 100X worse Area up to 10 100X greater February 8 2006 Kuon Rose FPGA2006 Do we really know how to program these http csg csail mit edu 6 375 L01 9 Switching power around 12X worse Performance up 3 4X worse Still requires tremendous design Area 20 40X greater February 8 2006 effort at RTL level http csg csail mit edu 6 375 L01 10 Future could be different if we became 10X more productive in design This course is about new ways expressing behavior to reduce design complexity Let s take a look at the current CMOS technology Decentralize complexity Rule based specifications Guarded Atomic Actions Let us think about one rule at a time Formalize composition Modules with guarded interfaces Automatically manage and ensure the correctness of connectivity i e correct by construction methodology Retain resilience to changes in design or layout e g compute latency s Promote regularity of layout at macro level February 8 2006 http csg csail mit edu 6 375 L01 11 February 8 2006 http csg csail mit edu 6 375 L01 12 FET Field Effect Transistor Simplified FET Model A four terminal device gate source drain bulk Binary logic values represented by voltages gate Surface of wafer Source diffusion Eh Ev inversion happens here High Supply Voltage Low Ground Voltage Drain diffusion S G bulk D Reverse side of wafer D Inversion A vertical field creates a channel between the source and drain G S Conduction If a channel exists a horizontal field causes a drift current from the drain to the source February 8 2006 L01 13 http csg csail mit edu 6 375 PFET connects S and D when G low 0V NFET connects D and S when G high VDD G PFET only good at pulling up G NFET only good at pulling down Ground GND 0V Parallel PMOS Transistors P Diffusion VDD in N well A B A B A B B B A A A B Poly wire connects PMOS NMOS gates When both A and B are high output is low When either A or B is low output is high Output on Metal 1 Metal 1 Diffusion Contact GND February 8 2006 L01 14 http csg csail mit edu 6 375 NAND Gate Layout NAND Gate A B February 8 2006 Supply Voltage VDD http csg csail mit edu 6 375 L01 15 February 8 2006 http csg csail mit edu 6 375 A B N Diffusion Series NMOS Transistors L01 16 Exponential growth Moore s Law Design Rules Exclusion rule Surround rule Extension rules Intel 8086 1978 33mm2 10Mhz 29K transistors 3u Intel 8080A 1974 3Mhz 6K transistors 6u Intel 80286 1982 47mm2 12 5Mhz 134K transistors 1 5u Intel 386DX 1985 43mm2 33Mhz 275K transistors 1u Width rules Spacing rules An abstraction of the fabrication process that specify various geometric constraints on how different masks can be drawn Design rules can be absolute measurements e g in nm or scaled to an abstract unit the lambda The value of lambda depends on the manufacturing process finally used February 8 2006 http csg csail mit edu 6 375 Intel 486 1989 81mm2 50Mhz 1 2M transistors 8u Intel Pentium 1993 1994 1996 295 147 90mm2 66Mhz 3 1M transistors 8u 6u 35u Shown with approximate relative sizes Shown with approximate relative sizes L01 17 February 8 2006 Intel Pentium II 1997 203mm2 104mm2 300 333Mhz 7 5M transistors 35u 25u http www intel com intel intelis museum exhibit hist micro hof hof main htm http csg csail mit edu 6 375 L01 18 Hardware Design Abstraction Levels IBM Power 5 130nm SOI CMOS with Cu 389mm2 2GHz 276 million transistors Dual processor cores 1 92 MB on chip L2 cache 8 way superscalar 2 way simultaneous multithreading Application Algorithm Unit Transaction Level UTL Model Guarded Atomic Actions
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