1February 25, 2008 http://csg.csail.mit.edu/6.375 L08-1Modeling ProcessorsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyFebruary 25, 2008L08-2http://csg.csail.mit.edu/6.375The PlanNon-pipelined processor⇐Two-stage asynchronous pipelineTwo-stage synchronous pipelineSome understanding of simple processor pipelines is needed to follow this lecture2February 25, 2008L08-3http://csg.csail.mit.edu/6.375Instruction settypedef enum {R0;R1;R2;…;R31} RName;An instruction set can be implemented using many different microarchitecturestypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct {RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName value; RName addr;} Store} Instr deriving(Bits, Eq);typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;February 25, 2008L08-4http://csg.csail.mit.edu/6.375Tagged Unions: Bit Representation00 dst src1 src201 cond addr10 dst addr11 dst immtypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct {RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName dst; Immediate imm;} AddImm;} Instr deriving(Bits, Eq);Automatically derived representation; can be customized by the user written pack and unpack functions3February 25, 2008L08-5http://csg.csail.mit.edu/6.375Non-pipelined Processorfetch & execute pciMem dMemrfCPUmodule mkCPU#(Mem iMem, Mem dMem)();Reg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();Instr instr = iMem.read(pc); Iaddress predIa = pc + 1;rule fetch_Execute ...endmoduleFebruary 25, 2008L08-6http://csg.csail.mit.edu/6.375Non-pipelined processor rulerule fetch_Execute (True);case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}: beginrf.upd(rd, rf[ra]+rf[rb]);pc <= predIaendtagged Bz {cond:.rc,addr:.ra}: begin pc <= (rf[rc]==0) ? rf[ra] : predIa; endtagged Load {dest:.rd,addr:.ra}: beginrf.upd(rd, dMem.read(rf[ra]));pc <= predIa;endtagged Store {value:.rv,addr:.ra}: begindMem.write(rf[ra],rf[rv]);pc <= predIa;endendcaseendruleAssume “magic memory”, i.e. responds to a read request in the same cycle and a write updates the memory at the end of the cycle4February 25, 2008L08-7http://csg.csail.mit.edu/6.375The PlanNon-pipelined processorTwo-stage asynchronous pipeline ⇐Two-stage synchronous pipelineFebruary 25, 2008L08-8http://csg.csail.mit.edu/6.375Processor Pipelines and FIFOsfetchexecuteiMemrfCPUdecodememorypcwrite-backdMemIt is better to think in terms of FIFOs as opposed to pipeline registers. We will present implementations in terms of both, i.e., FIFOs and pipeline Registers5February 25, 2008L08-9http://csg.csail.mit.edu/6.375interface SFIFO#(type t, type tr);method Action enq(t); // enqueue an itemmethod Action deq(); // remove oldest entrymethod t first(); // inspect oldest itemmethod Action clear(); // make FIFO emptymethod Bool find(tr); // search FIFOendinterfaceSFIFO (glue between stages)n = # of bits neededto represent thevalues of type “t“m = # of bits neededto represent thevalues of type “tr"not fullnot emptynot emptyrdyenabnnrdyenabrdyenqdeqfirstSFIFOmoduleclearenabfindmboolFebruary 25, 2008L08-10http://csg.csail.mit.edu/6.375Two-Stage Pipeline fetch & decodeexecutepcrfCPUbumodule mkCPU#(Mem iMem, Mem dMem)(Empty);Reg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();SFIFO#(InstTemplate, RName) bu<- mkSFifo(findf);Instr instr = iMem.read(pc);Iaddress predIa = pc + 1;InstTemplate it = bu.first();rule fetch_decode ...endmodule6February 25, 2008L08-11http://csg.csail.mit.edu/6.375Instructions & Templatestypedef union tagged { struct {RName dst; Value op1; Value op2} EAdd;struct {Value cond; Iaddress tAddr} EBz;struct {RName dst; Daddress addr} ELoad;struct {Value data; Daddress addr} EStore;} InstTemplate deriving(Eq, Bits);typedef union tagged {struct {RName dst; RName src1; RName src2} Add;struct {RName cond; RName addr} Bz;struct {RName dst; RName addr} Load;struct {RName value; RName addr} Store;} Instr deriving(Bits, Eq);typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;February 25, 2008L08-12http://csg.csail.mit.edu/6.375Rules for Add rule decodeAdd(instr matches Add{dst:.rd,src1:.ra,src2:.rb})bu.enq (EAdd{dst:rd,op1:rf[ra],op2:rf[rb]});pc <= predIa;endrulerule executeAdd(it matches EAdd{dst:.rd,op1:.va,op2:.vb})rf.upd(rd, va + vb);bu.deq();endrulefetch & decodeexecutepcrfCPUbu7February 25, 2008L08-13http://csg.csail.mit.edu/6.375Fetch & Decode Rule: Reexaminedfetch & decodeexecutepcrfCPUburule decodeAdd (instr matches Add{dst:.rd,src1:.ra,src2:.rb})bu.enq (EAdd{dst:rd, op1:rf[ra], op2:rf[rb]});pc <= predIa;endruleFebruary 25, 2008L08-14http://csg.csail.mit.edu/6.375Fetch & Decode Rule: correctedfetch & decodeexecutepcrfCPUburule decodeAdd (instr matches Add{dst:.rd,src1:.ra,src2:.rb}bu.enq (EAdd{dst:rd, op1:rf[ra], op2:rf[rb]});pc <= predIa;endrule&&& !bu.find(ra) &&& !bu.find(rb))8February 25, 2008L08-15http://csg.csail.mit.edu/6.375Rules for Branch rule decodeBz(instr matches Bz{cond:.rc,addr:.addr}) &&&!bu.find(rc) &&& !bu.find(addr));bu.enq (EBz{cond:rf[rc],addr:rf[addr]});pc <= predIa;endrulerule bzTaken(it matches EBz{cond:.vc,addr:.va}) &&&(vc==0));pc <= va; bu.clear(); endrulerule bzNotTaken (it matches EBz{cond:.vc,addr:.va}) &&&(vc != 0));bu.deq; endrulefetch & decodeexecutepcrfCPUbuFebruary 25, 2008L08-16http://csg.csail.mit.edu/6.375The Stall SignalBool stall =case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}: return (bu.find(ra) || bu.find(rb));tagged Bz {cond:.rc,addr:.addr}: return (bu.find(rc) || bu.find(addr));tagged Load {dst:.rd,addr:.addr}: return (bu.find(addr));tagged Store {value:.v,addr:.addr}: return (bu.find(v)) || bu.find(addr));endcase;Need to extend the fifo interface with the “find” method where “find” searches the fifo to see if a register is going to be updated9February 25, 2008L08-17http://csg.csail.mit.edu/6.375Parameterization: The Stall Functionfunction Bool stallfunc (Instr instr, SFIFO#(InstTemplate, RName) bu); case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}: return (bu.find(ra) || bu.find(rb));tagged Bz {cond:.rc,addr:.addr}: return (bu.find(rc) || bu.find(addr));tagged Load {dst:.rd,addr:.addr}: return (bu.find(addr));tagged Store
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