M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G YDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE6.375 Complex Digital SystemsSpring 2008 - Quiz - March 21, 200880 MinutesNAME: SCORE:Please write your name on every page of the quiz.Not all questions are of equal difficulty, so look over the entire quiz and budget your time carefully.Please carefully state any assumptions you make.Enter your answers in the spaces provided below. If you need extra room for an answer or forscratch work, you may use the back of each page but please clearly indicate where your answer islocated.You must not discuss the quiz’s contents with other students who have not yet takenthe quiz. If, prior to taking it, you are inadvertently exposed to material in a quiz —by whatever means — you must immediately inform the instructor or a TA.Points ScoreProblem 1 20Problem 225Problem 3 25Problem 4 10Problem 5 206.375 Quiz, Spring 2008 Name: 2Problem 1 : Throughput (20 total points)Ben Bitdiddle made a dual upcounter:using the following code:module temp();Reg#(Bit#(1)) stage <- mkReg(0);FIFO#(int) fifoA <- mkFIFO1();FIFO#(int) fifoB <- mkFIFO1();rule init (stage == 0);fifoA.enq(1);fifoB.enq(1);stage <= 1;endrulerule inc1 (stage == 1);let temp = fifoA.first();fifoA.deq();$display("Inc1: %d", temp);fifoB.enq(temp+1);endrulerule inc2 (stage == 1);let temp = fifoB.first();fifoB.deq();$display("Inc2: %d", temp);fifoA.enq(temp+1);endrulerule exit ((fifoA.first() == 6) || (fifoB.first() == 6));$finish();endruleendmoduleHe was expecting to see the following display:Inc1: 1 Inc2: 1 Inc1: 2 Inc2: 2 Inc1: 3 Inc2: 3 Inc1: 4 Inc2: 4 Inc1: 5 Inc2: 56.375 Quiz, Spring 2008 Name: 31.1 (10 poi nts)The code compiled, but on simulation, he did not see any display statements. Why is the code notexecuting correctly?1.2 (10 poi nts)Modify the code to get the desired execution. You can use library elements such as those used inthe labs.6.375 Quiz, Spring 2008 Name: 4Problem 2 : Bluespec Semantics (25 total points)Consider the code given below:module sem();Reg#(int) count <- mkReg(1);Reg#(int) a <- mkReg(1);Reg#(int) b <- mkReg(2);Reg#(int) c <- mkReg(3);rule counter (True);count <= count + 1;endrulerule mod1 (True);a <= b + c;endrulerule mod2 (True);b <= c + count;endrulerule mod3 (True);c <= b + count;endrulerule exit (count >= 4);$finish();endruleendmodule2.1 (6 poi nts)What are the sequential composability conditions deduced by the compiler?2.2 (9 poi nts)Using the above conditions, assume an overall order and determine the values of all the stateelements at finish.6.375 Quiz, Spring 2008 Name: 52.3 (10 poi nts)Modify the code such that all the rules fire every cycle in the following order:counter | mod1 < mod2 < mod3 < exitYou can use EHRs of any order.6.375 Quiz, Spring 2008 Name: 6Problem 3 : Bluespec Synthesis (25 total points)Consider the code shown below:module mkMultBySixDyn(Foo#(int));Reg#(int) a <- mkReg(0);Reg#(int) x <- mkReg(0);Reg#(int) count <- mkReg(0);rule mulDyn (count>0 && count<6);count <= count+1;a <= a+x;endrulemethod Action put (int y) if (count==0);a <= y; x <= y;count <= 1;endmethodmethod ActionValue#(int) get if (count==6);count <= 0;return a;endmethodendmodule3.1: 15 pointsSketch the hardware produced on compiling this code. Label the interface signals, scheduling logicand signals corresponding to CANFIRE mulDyn and WILL FIRE mulDyn.6.375 Quiz, Spring 2008 Name: 73.2: 10 pointsThe rule mulDyn is replaced by the following rule:rule mulStat (count>0 && count<6);for(int i = 1; i<6; i++)if(count==i)begincount <= i+1; a <= a+x;endendruleHow does this change affect the hardware generated? Which implementation mulDyn or mulStathas more adders? More muxes? Compare the overall area and critical paths of the implementations.6.375 Quiz, Spring 2008 Name: 8Problem 4 : RC Delay (10 points)Assume you have an inverter (nmos width = 1 µm, pmos width = 2 µm) driving an interconnectof length 0.2 mm as shown in the figure. The interconnect has an inverter (nmos width = 5 µm,pmos width = 10 µm) at the other end which drives a flipflop whose input capacitance is 20 fF.Calculate the delay of the circuit from point A to point B (see figure). You can use a π model (asshown in the attached slide) for the bitline and assume that the transistors turn on after one RCtime constant. The process parameters are given in the table below.Process Parameters ValuePMOS gate capacitance per µm of transistor width 1.5fF/µmNMOS gate capacitance per µm of transistor width 1.5fF/µmPMOS drain capacitance p e r µm of transistor width 0.3fF/µmNMOS drain capacitance per µm of transistor width 0.3fF/µmPMOS effective on resistance 6.6kΩµmNMOS effective on resistance 3.3kΩµmMetal 2 wire resistance per µm of length 0.4Ω/µmMetal 2 wire capacitance per µm of length 0.2fF/µm6.375 Quiz, Spring 2008 Name: 9Problem 5 : Power (20 total points)The following two unit designs implement the same s ignal processing function, with the followingperformance characteristics.Unit Throughput Vdd Energy/Task(million (volts) (nanojoules)tasks/sec)Unit 1 20 1.2 5Unit 2 10 1.2 3The following table lists the effect of changing supply voltage on circuit delay and energy peroperation, normalized to that at 1.2V.Vdd Delay Energy/Task1.5 0.7 1.91.4 0.8 1.51.3 0.9 1.21.2 1.0 1.01.1 1.2 0.81.0 1.5 0.60.9 2.0 0.40.8 10.0 0.30.7 non-functional non-functionala) Which unit is the most energy efficient for a minimum throughput of million 12.5 tasks/second?Show your work. 6 points6.375 Quiz, Spring 2008 Name: 10b) Which unit gives the highest performance at a maximum power dissipation of 30mW? Showyour work. 6 pointsc) Assume the signal processing function is perfectly parallelizable. What is the lowest powerparallel configuration to process 20 million tasks/second? Ignore the area cost. List which unit isused, the operating voltage, and the number of parallel instances. 8
View Full Document
Unlocking...