1February 8, 2006 http://csg.csail.mit.edu/6.375/ L01-16.375 Complex Digital SystemSpring 2006Lecturer: Arvind TAs: Chris Batten & Mike PellauerAssistant: Sally LeeFebruary 8, 2006 L01-2http://csg.csail.mit.edu/6.375/Do we need more chips (ASICs)?ASIC=Application Specific ICSome exciting possibilities based on research @ CSAIL2February 8, 2006 L01-3http://csg.csail.mit.edu/6.375/Content distribution andcustomer serviceInteractive, lifelike avatars as actors, news anchors, and customer service representatives Source: Computer Science and Artificial Intelligence Laboratory at MIT (CSAIL)February 8, 2006 L01-4http://csg.csail.mit.edu/6.375/Ubiquitous, behind-the-scenes computingComputer interfaces woven tightly into the environment Source: Computer Science and Artificial Intelligence Laboratory at MIT (CSAIL)3February 8, 2006 L01-5http://csg.csail.mit.edu/6.375/Source: http://www.intel.com/technology/silicon/mooreslaw/index.htmWhat’s required?ICs with dramatically higher performance, optimized for applicationsand at a size and power to deliver mobility;cost to address mass consumer marketsFebruary 8, 2006 L01-6http://csg.csail.mit.edu/6.375/Current Cellphone ArchitectureComms. ProcessingApplication ProcessingWLAN RFWLAN RFWLAN RFWCDMA/GSM RFTwo chips, each with an ARM general-purpose processor (GPP) and a DSPTI OMAP 2420COMPLEX4February 8, 2006 L01-7http://csg.csail.mit.edu/6.375/Chip design has become too risky a business Ever increasing size and complexity Microprocessors: 100M gates ⇒ 1000M gates ASICs: 5M to 10M gates ⇒ 50M to 100M gatesEver increasing costs and design team sizes > $10M for a 10M gate ASIC > $1M per re-spin in case of an error (does not include the redesign costs, which can be substantial)18 months to design but only an eight-month selling opportunity in the market Fewer new chip-starts every year Looking for alternatives, e.g., FPGA’s⇒February 8, 2006 L01-8http://csg.csail.mit.edu/6.375/Designer’s DilemmaSub-optimal implementations!Designer must take shortcuts Conservative design No time for exploration Educated guess & code Gates are free mentalityConstants 10-30 person design team size 18 month design schedule Design flow -- unchanged for 10+ years!ASIC Complexity 2000: 1M+ logic gates 2005: 10M+ logic gates 2010: 100M+ logic gates63.53.322,391Static (2)99.999.963.5MemoryUtil (%)3.608,898Static4.7015,910Linear3.678,170CircularSpeed(ns)Area(gates)LPM PipelineWhat happens when a designer must implement a 1M gate block?Alternatives?[ICCAD’04]LPM Pipeline example: Which is best?5February 8, 2006 L01-9http://csg.csail.mit.edu/6.375/One prevailing viewpoint:A sea of general purpose processorsAdvantages Easier to scale hardwaredesign as complexityis contained within processors Easy to program and debug complex applicationsIBM/Sony Cell Processor Do we really know how to program these?Disadvantages (as compared to an ASIC) Power ~100-1000X worse Performance up to ~100X worse Area up to ~10-100X greaterFebruary 8, 2006 L01-10http://csg.csail.mit.edu/6.375/Another popular “platform” vision: Field-Programmable Gate ArraysAdvantages Dramatically reduce the cost of errors Remove the reticlecosts from each designDisadvantages (as compared to an ASIC)[Kuon & Rose, FPGA2006] Switching power around ~12X worse Performance up 3-4X worse Area 20-40X greaterStill requires tremendous design effort at RTL level6February 8, 2006 L01-11http://csg.csail.mit.edu/6.375/Future could be different if we became 10X more productive in designThis course is about new ways expressing behavior to reduce design complexityDecentralize complexity: Rule-based specifications (Guarded Atomic Actions) Let us think about one rule at a timeFormalize composition: Modules with guarded interfaces Automatically manage and ensure the correctness of connectivity, i.e., correct-by-construction methodology Retain resilience to changes in design or layout, e.g. compute latency Δ’s Promote regularity of layout at macro levelFebruary 8, 2006 L01-12http://csg.csail.mit.edu/6.375/Let’s take a look at the current CMOS technology...7February 8, 2006 L01-13http://csg.csail.mit.edu/6.375/FET = Field-Effect TransistorA four terminal device (gate, source, drain, bulk)EhInversion: A vertical field creates a channel between the source and drain.Conduction: If a channel exists, a horizontal field causes a drift current from the drain to the source.EvSource diffusionDrain diffusiongatebulkSurface of waferReverse side of waferinversionhappens hereFebruary 8, 2006 L01-14http://csg.csail.mit.edu/6.375/Simplified FET ModelGPFET connects S and D when G=“low”=0VGNFET connects D and S when G=“high”=VDDSDSDGPFET only good at pulling upGNFET only good at pulling downSupply Voltage = VDDGround = GND = 0VBinary logic values represented by voltages:“High” = Supply Voltage, “Low” = Ground Voltage8February 8, 2006 L01-15http://csg.csail.mit.edu/6.375/NAND GateAB(A.B) When both A and B are high, output is low When either A or B is low, output is highBA(A.B)February 8, 2006 L01-16http://csg.csail.mit.edu/6.375/NAND Gate LayoutAB(A.B)Series NMOS TransistorsParallel PMOS TransistorsMetal 1-Diffusion ContactP-Diffusion (in N-well)N-DiffusionGNDVDDAB(A.B)Poly wire connects PMOS & NMOS gatesOutput on Metal-19February 8, 2006 L01-17http://csg.csail.mit.edu/6.375/Design RulesExtensionrulesWidthrulesExclusion ruleSurround ruleSpacing rulesAn abstraction of the fabrication process that specify various geometric constraints on how different masks can be drawnDesign rules can be absolute measurements (e.g. in nm) or scaled to an abstract unit, the lambda. The value of lambda depends on the manufacturing process finally used. February 8, 2006 L01-18http://csg.csail.mit.edu/6.375/Exponential growth: Moore’s LawIntel 8080A, 19743Mhz, 6K transistors, 6uIntel 8086, 1978, 33mm210Mhz, 29K transistors, 3uIntel 80286, 1982, 47mm212.5Mhz, 134K transistors, 1.5uIntel 386DX, 1985, 43mm233Mhz, 275K transistors, 1u Intel 486, 1989, 81mm250Mhz, 1.2M transistors, .8uIntel Pentium, 1993/1994/1996, 295/147/90mm266Mhz, 3.1M transistors, .8u/.6u/.35uIntel Pentium II, 1997, 203mm2/104mm2300/333Mhz, 7.5M transistors, .35u/.25uhttp://www.intel.com/intel/intelis/museum/exhibit/hist_micro/hof/hof_main.htmShown with approximate relative sizesShown with approximate relative sizes10February 8, 2006
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