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MIT 6 375 - Lab 5: Pipelining an SMIPSv2 Processor: Part I

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IntroductionThe Processor InfrastructureGetting StartedThe Source CodeThe SceMi SetupBuilding the ProjectUsing the Test BenchDebugging with TracesAssembly TestsBenchmarksThe Unpipelined ProcessorPipelining the ProcessorMoving Register Updates to the Writeback StageLetting Writeback Run IndependentlyLetting PCGen and Exec Run IndependentlySMIPSv2 Instruction SetLab 5: Pipelining an SMIPSv2 Processor: Part I6.375 Laboratory 5Assigned: March 4, 2011Due: March 11, 20111 IntroductionIn this laboratory assignment and the next you will be provided with an unpipelined three stageSMIPSv2 processor in Bluespec which you must pipeline to acheive good performance. Obtaininggood performance requires a solid understanding of how Bluespec schedules rules, something youshould be an expert at by the time you complete these labs. For this first lab your task is to producean elastic pipelined design which functions correctly. The next lab will focus on achieving adequateperformance in the pipeline.This lab handout describes the processor infrastructure, including how to build and run the processorto determine if it functions correctly and how well it performs, advice on how to debug the processor,the initial unpipelined processor design, and detailed steps you should take to successfully pipelinethe unpipelined processor.2 The Processor InfrastructureA large amount of work has already been done for you in setting up the infrastructure to run, test,evaluate performance, and debug your SMIPSv2 processor in simulation and on the FPGA. Thissection describes that infrastructure.Appendix A inclues a reference on the SMIPSv2 instruction set your processor supports.2.1 Getting StartedUpdate your local repository with the code from the lab 5 harness. Add the 6.375 course locker,source the setup script, navigate to the directory which contains the audio/ folder from previouslabs, and run$ tar xf /mit/6.375/lab-harnesses/lab5-harness.tar.gzThis will create a directory called smips with the code for this lab and the next. To save yourchanges to your local repository, run$ git add smips$ git commit -m "lab5 initial checkin"InstCacheBlockingDataCacheBlockingProcessorCoreMemArbStatsToHostMMemFigure 1: Processor Core2.2 The Source CodeFigure 1 shows the processor core described by the source code in the src/ directory. The processoris connected to instruction and data caches. The instruction and data caches interface to the mainoff-core memory through the memory arbiter. The processor core and both caches collect and exposestatistics about the runtime behavior. The processor’s toHost register used in the MTC0 instructionis also exposed.The source code implementing the core and all of its components is split into files in the src/directory as follows.Core.bsv The top level core. This instantiates the memory arbiter, instruction and data caches,and the processor.DataCacheBlocking.bsv Implementation of the data cache.InstCacheBlocking.bsv Implementation of the instruction cache.MemArb.bsv Implementation of the memory arbiter which arbitrates requests to main memory fromthe instruction and data caches.MemTypes.bsv Common types related to memory.ProcTypes.bsv Common types related to the processor.Processor.bsv The actual processor. The processor provided is a three stage unpipelined processordescribed in more detail in section 3. This is where the majority, if not all, of your modificationsshould be made for this lab.SFIFO.bsv Implementations of searchable FIFOs for use in pipelining the processor.Trace.bsv Definition of the Trace typeclass used for trace output. Tracing is described in moredetail in section 2.6.2.3 The SceMi SetupFigure 2 shows the SceMi setup for the lab. The SceMiLayer instantiates the core shown in figure1 and SceMi ports for the core’s main memory client, stats, and toHost interface. The SceMiLayer2SceMiLayerHostProcessorMain MemMain LoopTestBenchCoreStatsToHostBridgeMMemHardwareSoftwareRstFigure 2: SceMi Setupalso provides a SceMi port for reseting the core from the test bench, allowing multiple programs tobe run on the Processor without reprogramming the FPGA.The core’s main memory is implemented in the software test bench running on the host for conve-nience. Cache misses will result in a memory request being sent accross the SceMi link.Source code for the SceMiLayer and Bridge are in the scemi/ directory. The SceMi link goes overa TCP bridge for simulation and a PCIe bridge when running on the actual FPGA.2.4 Building the ProjectThe file sim/project.bld describes how to build the project using the build command which ispart of the Bluespec installation. Run build --doc for more information on the build command.The full project, including hardware and testbench, can be rebuilt from scratch by running thecommand build -v from the sim/ directory.The file sim/sim.bspec is a Bluespec Workstation project file that can be used to build the projectfrom within the Bluespec Workstation rather than building from the command line. To build theproject in the Workstation, run from the sim/ directory:bluespec sim.bspec&This opens up the Workstation. From there you can compile and link to generate the two executablesbsim dut and tb. The executable bsim dut simulates the hardware; tb is the test bench.The fpga/ directory contains its own project.bld and fpga.bspec for building the project for theFPGA. Building for the FPGA includes running synthesis, map, and place-and-route, and takes onthe order of an hour to complete. When the build has completed, the FPGA can be programmedusing the ../tools/program fpga command on the FPGA servers. Building for FPGA also createsa tb executable for the test bench.32.5 Using the Test BenchThe test bench is software run on the host processor which interacts with the SMIPSv2 processorover the SceMi link, as shown in figure 2. The test bench loads a program for the SMIPSv2 processorto execute, waits for the processor to send a non-zero value over the toHost interface, then collectsand displays whatever statistics were gathered in the core when executing the SMIPSv2 program.The SMIPSv2 programs are specified in Verilog Memory Hex (vmh) format. The data/ directorycontains a number of programs in this format. It is also possible to use the smips-gcc toolchain tocompile your own c programs to this format. Ask the TA for more info if you are interested in doingso.The test bench takes a single command line argument which is the .vmh file with the program torun on the SMIPSv2


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MIT 6 375 - Lab 5: Pipelining an SMIPSv2 Processor: Part I

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