Verilog 2 - Design ExamplesCourse administrative notesVerilog Design ExamplesA module can be described in many different ways but it should not matter from outsidemux4: Gate-level structural Verilogmux4: Using continuous assignmentsmux4: Behavioral stylemux4: Using always blockmux4: Always block permit more advanced sequential idiomsParameterized mux4flip-flopsflip-flops with resetRegisterRegister in terms of FlipflopsStatic Elaboration: GenerateSlide 16GCD in CBehavioral GCD in VerilogYou have to be careful in using such behavioral modelsDeriving an RTL model for GCDThe first step is to carefully design an appropriate port interfaceNext develop a datapath which has the proper functional unitsNext develop a datapath which has the proper functional unitsSlide 24Finally add the control unit to sequence the datapathDatapath module interfaceConnect the modulesConnect the modules ...Control unit requires a simple state machine for valid/ready signalsImplementing the control logic finite state machine in VerilogImplementing the control signal outputs for the finite state machineImplementing the state transitions for the finite state machineRTL test harness requires proper handling of the ready/valid signalsWe can compare the behavioral and RTL implementations to verify correctnessSlide 35SMIPS is a simple MIPS ISA which includes three variantsSMIPSv1 ISAThe first step is to carefully design an appropriate port interfaceSMIPSv1 Block Diagram How do we start implementing?Let’s identify the memories, datapaths, and random logic in our SMIPSv1 designSlide 41SMIPSv1 datapath interface contains controls signals and memory data busesRegister file with two combinational read ports and one write portVerilog for SMIPSv1 control logicSlide 45Take away pointsVerilog 2 - Design Examples6.375 Complex Digital SystemsFebruary 12, 20076.375 Spring 2007 • L03 Verilog 2 - Design Examples • 2Course administrative notes•If you did not receive an email over the weekend concerning the course then you are not on the student mailing list - please email 6.375-staff•Lab 1 is due Friday, February 16–2-stage SMIPSv2 processor RTL checked into CVS–Critical thinking questions; hardcopy due in class6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 3Verilog Design Examples•Building blocks•Greatest Common Divisor•Unpipelined SMIPSv1 processorA module can be described in many different ways but it should not matter from outsideExample: mux46.375 Spring 2007 • L03 Verilog 2 - Design Examples • 5module mux4( input a, b, c, d, input [1:0] sel, output out ); wire [1:0] sel_b; not not0( sel_b[0], sel[0] ); not not1( sel_b[1], sel[1] ); wire n0, n1, n2, n3; and and0( n0, c, sel[1] ); and and1( n1, a, sel_b[1] ); and and2( n2, d, sel[1] ); and and3( n3, b, sel_b[1] ); wire x0, x1; nor nor0( x0, n0, n1 ); nor nor1( x1, n2, n3 ); wire y0, y1; or or0( y0, x0, sel[0] ); or or1( y1, x1, sel_b[0] ); nand nand0( out, y0, y1 );endmodule mux4: Gate-level structural Verilogsel[0]sel[1]cadbout6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 6module mux4( input a, b, c, d input [1:0] sel, output out ); wire out, t0, t1; assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) ); assign t1 = ~( (sel[1] & d) | (~sel[1] & b) ); assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );endmodule mux4: Using continuous assignmentsmodule mux4( input a, b, c, d input [1:0] sel, output out ); wire out, t0, t1; assign t0 = ~( (sel[1] & c) | (~sel[1] & a) ); assign t1 = ~( (sel[1] & d) | (~sel[1] & b) ); assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );endmodule The order of these continuous assignment statements does not matter. They essentially happen in parallel!Language defined operators6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 7mux4: Behavioral style// Four input multiplexermodule mux4( input a, b, c, d input [1:0] sel, output out ); assign out = ( sel == 0 ) ? a : ( sel == 1 ) ? b : ( sel == 2 ) ? c : ( sel == 3 ) ? d : 1’bx;endmodule If input is undefined we want to propagate that information.6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 8mux4: Using always block module mux4( input a, b, c, d input [1:0] sel, output out ); reg out, t0, t1; always @( a or b or c or d or sel ) begin t0 = ~( (sel[1] & c) | (~sel[1] & a) ); t1 = ~( (sel[1] & d) | (~sel[1] & b) ); out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) ); endendmodule The order of these procedural assignment statements does matter.They essentially happen sequentially!6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 9mux4: Always block permit more advanced sequential idiomsmodule mux4( input a, b, c, d input [1:0] sel, output out ); reg out; always @( * ) begin if ( sel == 2’d0 ) out = a; else if ( sel == 2’d1 ) out = b else if ( sel == 2’d2 ) out = c else if ( sel == 2’d3 ) out = d else out = 1’bx; end endmodule module mux4( input a, b, c, d input [1:0] sel, output out ); reg out; always @( * ) begin case ( sel ) 2’d0 : out = a; 2’d1 : out = b; 2’d2 : out = c; 2’d3 : out = d; default : out = 1’bx; endcase end endmodule Typically we will use always blocks only to describe sequential circuits6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 10module mux4( input a, b, c, d input [1:0] sel, output out ); wire out, t0, t1; assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) ); assign t1 = ~( (sel[1] & d) | (~sel[1] & b) ); assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );endmodule Parameterized mux4module mux4 #( parameter WIDTH = 1 ) ( input[WIDTH-1:0] a, b, c, d input [1:0] sel, output[WIDTH-1:0] out ); wire [WIDTH-1:0] out, t0, t1; assign t0 = (sel[1]? c : a); assign t1 = (sel[1]? d : b); assign out = (sel[0]? t0: t1);endmodule Instantiation Syntaxmux4#(32) alu_mux( .a (op1), .b (op2), .c (op3), .d (op4), .sel (alu_mux_sel), .out (alu_mux_out) );default valueParameterization is a good practice for reusable modules6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 11flip-flopsDQXnext_XclkDQXnext_Xclkenablemodule FF (input clk, input d, input en, output q);always @( posedge clk ) begin if ( en ) q <= d; endendmodulemodule FF0 (input clk, input d, output q);always @( posedge clk ) begin q <= d; endendmodule6.375 Spring 2007 • L03 Verilog 2 - Design Examples • 12flip-flops with
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