Modeling ProcessorsInstruction setDeriving BitsTagged Unions: Bit RepresentationThe PlanNon-pipelined ProcessorNon-pipelined processor ruleRegister FileSlide 9Two-stage Inelastic PipelineInstructions & TemplatesFetch & Decode Action Fills the buReg with a decoded instructionExecute Action: Reads buReg and modifies state (rf,dMem,pc)Issues with buRegInelastic Pipeline first attemptExecutePipeline HazardsStall conditionThe Stall Function Decides if instruction instr should stall given the state of the buRegInelastic Pipeline correctedBypassingGeneration of bypass register valueBypassing values to FetchNew fetchActionUpdated newItSlide 26The stall function for the Inelastic pipelineInelastic PipelinesModeling ProcessorsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyMarch 1, 2010 http://csg.csail.mit.edu/6.375 L08-1Instruction setMarch 1, 2010http://csg.csail.mit.edu/6.375typedef enum {R0;R1;R2;…;R31} RName;An instruction set can be implemented using many different microarchitecturestypedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName valueR; RName addrR;} Store} Instr deriving(Bits, Eq);typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;L08-2Deriving BitsTo store datatypes in register, fifo, etc. we need to know how to represent them as bits (pack) and interpret their bit representation (unpack)Deriving annotation automatically generates the “pack” and “unpack” operations on the type (simple concatenation of bit representations of components)It is possible to customize the pack/unpack operations to any specific desired representationMarch 1, 2010http://csg.csail.mit.edu/6.375typedef struct { … } Foo deriving (Bits);L08-3Tagged Unions: Bit RepresentationMarch 1, 2010http://csg.csail.mit.edu/6.37500 dst src1 src201 condR addrR10 dst addrR11 dst immtypedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName dst; Immediate imm;} AddImm;} Instr deriving(Bits, Eq);Automatically derived representation; can be customized by the user written pack and unpack functionsL08-4The PlanNon-pipelined processorTwo-stage Inelastic pipelineTwo-stage Elastic pipeline – next lectureMarch 1, 2010http://csg.csail.mit.edu/6.375Some understanding of simple processor pipelines is needed to follow this lectureL08-5Non-pipelined ProcessorMarch 1, 2010http://csg.csail.mit.edu/6.375fetch & execute pc iMem dMemrfCPUmodule mkCPU#(Mem iMem, Mem dMem)(); Reg#(Iaddress) pc <- mkReg(0); RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();Instr instr = iMem.read(pc); Iaddress predIa = pc + 1; rule fetch_Execute ...endmoduleL08-6Non-pipelined processor ruleMarch 1, 2010http://csg.csail.mit.edu/6.375rule fetch_Execute (True); case (instr) matches tagged Add {dst:.rd,src1:.ra,src2:.rb}: begin rf.upd(rd, rf[ra]+rf[rb]); pc <= predIa end tagged Bz {condR:.rc,addrR:.ra}: begin pc <= (rf[rc]==0) ? rf[ra] : predIa; end tagged Load {dest:.rd,addrR:.ra}: begin rf.upd(rd, dMem.read(rf[ra])); pc <= predIa; end tagged Store {valueR:.rv,addrR:.ra}: begin dMem.write(rf[ra],rf[rv]); pc <= predIa; end endcaseendrulemy syntaxrf[r] rf.sub(r)Assume “magic memory”, i.e. responds to a read request in the same cycle and a write updates the memory at the end of the cyclePattern matchingL08-7Register FileHow many read ports?TwoHow many write ports?OneConcurrency properties?Must be able to do two reads and a write concurrentlyThe values produced must be as if reads precede the write (if any)March 1, 2010L08-8http://csg.csail.mit.edu/6.375The PlanNon-pipelined processorTwo-stage Inelastic pipeline Two-stage Elastic pipelineMarch 1, 2010http://csg.csail.mit.edu/6.375 L08-9Two-stage InelasticPipelineMarch 1, 2010http://csg.csail.mit.edu/6.375fetch & decodeexecutebuRegtime t0 t1 t2 t3 t4 t5 t6 t7 . . . .FDstage FD1FD2FD3FD4FD5EXstage EX1EX2EX3EX4EX5Actions to be performed in parallel every cycle:Fetch Action: Decodes the instruction at the current pc and fetches operands from the register file and stores the result in buRegExecute Action: Performs the action specified in buReg and updates the processor state (pc, rf, dMem)pc rf dMemL08-10rule InelasticPipeline2(True);fetchAction; executeAction; endruleInstructions & TemplatesMarch 1, 2010http://csg.csail.mit.edu/6.375typedef union tagged { struct {RName dst; Value op1; Value op2} EAdd; struct {Value cond; Iaddress tAddr} EBz; struct {RName dst; Daddress addr} ELoad; struct {Value val; Daddress addr} EStore;} InstTemplate deriving(Eq, Bits);typedef union tagged { struct {RName dst; RName src1; RName src2} Add; struct {RName condR; RName addrR} Bz; struct {RName dst; RName addrR} Load; struct {RName valueR; RName addrR} Store;} Instr deriving(Bits, Eq);buReg contains instruction templates, i.e., decoded instructionsL08-11Fetch & Decode ActionFills the buReg with a decoded instructionMarch 1, 2010http://csg.csail.mit.edu/6.375function InstrTemplate newIt(Instr instr); case (instr) matches tagged Add {dst:.rd,src1:.ra,src2:.rb}: return EAdd{dst:rd,op1:rf[ra],op2:rf[rb]}; tagged Bz {condR:.rc,addrR:.addr}: return EBz{cond:rf[rc],tAddr:rf[addr]}; tagged Load {dst:.rd,addrR:.addr}: return ELoad{dst:rd,addrR:rf[addr]}; tagged Store{valueR:.v,addrR:.addr}: return EStore{val:rf[v],addr:rf[addr]}; endcase endfunction buReg <= newIt(instr); L08-12Execute Action: Reads buReg and modifies state (rf,dMem,pc)March 1, 2010http://csg.csail.mit.edu/6.375case (buReg) matches tagged EAdd{dst:.rd,op1:.va,op2:.vb}: begin rf.upd(rd, va+vb); pc <= predIa; end tagged ELoad{dst:.rd,addr:.av}: begin rf.upd(rd, dMem.read(av)); pc <= predIa; end tagged EStore{val:.vv,addr:.av}: begin dMem.write(av, vv); pc <= predIa; end tagged EBz {cond:.cv,tAddr:.av}: if (cv != 0) then pc <= predIa; else begin pc <= av; Invalidate buReg endendcaseWhat does this mean?L08-13Issues with buRegMarch 1, 2010http://csg.csail.mit.edu/6.375fetch &
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