1February 4, 2009 http://csg.csail.mit.edu/6.375/ L01-16.375 Complex Digital SystemSpring 2009Lecturer: ArvindTA: K. Elliott FlemingAssistant: Sally LeeFebruary 4, 2009 L01-2http://csg.csail.mit.edu/6.375/Why take 6.375?Take 1We need a much greater variety of chips (ASICs)Why? Power savings: Specialized hardware for a video decoder (H.264) may consume 1/100thto 1/1000ththe power of a software implementation Cost Performance Size …ASIC = Application-Specific Integrated Circuit2February 4, 2009 L01-3http://csg.csail.mit.edu/6.375/Wide Variety of Products Rely on ASICsFebruary 4, 2009 L01-4http://csg.csail.mit.edu/6.375/Source: http://www.intel.com/technology/silicon/mooreslaw/index.htmWhat’s required?ICs with dramatically higher performance, optimized for applicationsand at a size and power to deliver mobilitycost to address mass consumer markets3February 4, 2009 L01-5http://csg.csail.mit.edu/6.375/Custom and Semi-Custom Hand-drawn transistors (+ some standard cells) High volume, best possible performance: used for most advanced microprocessorsStandard-Cell-Based ASICs High volume, moderate performance: Graphics chips, network chips, cell-phone chipsField-Programmable Gate Arrays Prototyping Low volume, low-moderate performance applications ASIC Design StylesDifferent design styles require different design tools and have vastly different chip development costFebruary 4, 2009 L01-6http://csg.csail.mit.edu/6.375/Exponential growth: Moore’s LawIntel 8080A, 19743Mhz, 6K transistors, 6uIntel 8086, 1978, 33mm210Mhz, 29K transistors, 3uIntel 80286, 1982, 47mm212.5Mhz, 134K transistors, 1.5uIntel 386DX, 1985, 43mm233Mhz, 275K transistors, 1u Intel 486, 1989, 81mm250Mhz, 1.2M transistors, .8uIntel Pentium, 1993/1994/1996, 295/147/90mm266Mhz, 3.1M transistors, .8u/.6u/.35uIntel Pentium II, 1997, 203mm2/104mm2300/333Mhz, 7.5M transistors, .35u/.25uhttp://www.intel.com/intel/intelis/museum/exhibit/hist_micro/hof/hof_main.htmShown with approximate relative sizesShown with approximate relative sizes4February 4, 2009 L01-7http://csg.csail.mit.edu/6.375/Intel Penryn (2007)Dual coreQuad-issue out-of-order superscalar processors6MB shared L2 cache45nm technology Metal gate transistors High-K gate dielectric410 Million transistors3+? GHz clock frequencyCould fit over 500 486 processors on same size die.February 4, 2009 L01-8http://csg.csail.mit.edu/6.375/But Design Effort is GrowingNvidia Graphics Processing Units02040608010012019931995199619971998199920002001200120022002Design Effort per Chip Transistors (M)Relative staffing on front-endRelative staffing on back-end9x growth in back-end staff5x growth in front-end staffFront-end is designing the logic (RTL)Back-end is fitting all the gates and wires on the chip; meeting timing specifications; wiring up power, ground, and clock5February 4, 2009 L01-9http://csg.csail.mit.edu/6.375/Design Cost Impacts Chip CostAn Altera studyNon-Recurring Engineering (NRE) costs for a 90nm ASIC is ~ $30M 59% chip design (architecture, logic & I/O design, product & test engineering) 30% software and applications development 11% prototyping (masks, wafers, boards)If we sell 100,000 units, NRE costs add $30M/100K = $300 per chip!Alternative: Use FPGAsHand-crafted IBM-Sony-Toshiba Cell microprocessor achieves 4GHz in 90nm, but at the development cost of >$400M February 4, 2009 L01-10http://csg.csail.mit.edu/6.375/Field-Programmable Gate Arrays (FPGAs)Arrays mass-produced but programmed by customer after fabrication Can be programmed by loading SRAM bits, or loading FLASH memoryEach cell in array contains a programmable logic functionArray has programmable interconnect between logic functionsOverhead of programmability makes arrays expensive and slow but startup costs are low, so much cheaper than ASIC for small volumes6February 4, 2009 L01-11http://csg.csail.mit.edu/6.375/FPGA Pros and ConsAdvantages Dramatically reduce the cost of errors Little physical design work Remove the reticle costs from each designDisadvantages (as compared to an ASIC)[Kuon & Rose, FPGA2006] Switching power around ~12X worse Performance up 3-4X worse Area 20-40X greaterStill requires tremendous design effort at RTL levelFebruary 4, 2009 L01-12http://csg.csail.mit.edu/6.375/What is needed to make hardware design easierExtreme IP reuse Multiple instantiations of a block for different performance and application requirements Packaging of IP so that the blocks can be assembled easily to build a large system (black box model)Ability to do modular refinementWhole system simulation to enable concurrent hardware-software development Need new methods and tools to raise the level of design“Intellectual Property”Bluespec7February 4, 2009 L01-13http://csg.csail.mit.edu/6.375/Bluespec: Enabling High-level SynthesisVCD outputDebussyVisualizationCBluesimCycleAccurateBluespec SystemVerilog sourceVerilog 95 RTLVerilog simBluespec CompilerRTL synthesisgatesFPGAPower estimation toolPower estimation toolwhat we did until last year in 6.375what we plan to do this yearFebruary 4, 2009 L01-14http://csg.csail.mit.edu/6.375/Why take 6.375?Take 2 - The new opportunity“Big” FPGAs have become widely available A multicore can be emulated on one FPGA but the programming model is RTL and not too many people design hardwareEnable the use of FPGAs via Bluespec8February 4, 2009 L01-15http://csg.csail.mit.edu/6.375/Some cool projects IBM PowerPC PrototypeIntel’s HAsim – Cycle-accurate performance modelsAirBlue – A new platform to experiment with wireless protocolsVideo decoder – H.264Hardware software co-generationFebruary 4, 2009 L01-16http://csg.csail.mit.edu/6.375/IBM: PowerPC Prototype K. Ekanadham, Jessica Tseng (IBM)Asif Khan, M. Vijayaraghavan (MIT)Goal: Implement a multithreaded, multicore, in-order PowerPC on an FPGA platform and boot Linux on it in 12 monthsTeam: 2(IBM) + 2(MIT) + Linux and FPGA helpThe team accomplished the goal- Bluespec PowerPC boots Linux on FPGAs in 10min;- 100M instructions to reach “Hello World”; - 15K lines of Bluespec generated 90K lines of VerilogIBM synthesized the generated Verilog using their tools in 40nm library– ran at 500MHz in the first try!Working on a public release…9February 4, 2009 L01-17http://csg.csail.mit.edu/6.375/HAsim: Performance modeling of CPUs Joel Emer … (Intel), M. Pellauer …(MIT)Intel Asim: Framework for execution-driven simulation Performance:
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