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MIT 6 375 - Automatic Placement and Routing using Cadence Encounter

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Automatic Placement and Routing using Cadence Encounter6.375 Tutorial 5February 12, 2007In this tutorial you will gain experience using Cadence Encounter to perform automatic placementand routing. A place+route tool takes a gate-level netlist as input and first determines how eachgate should be placed on the chip. It uses several heuristic algorithms to group related gatestogether and thus hopefully minimize routing congestion and wire delay. Place+route tools willfocus their effort on minimizing the delay through the critical path. To this end, these tools canresize gates, insert new buffers, and even perform local resynthesis. Place+route tools often haveadditional algorithms to help reduce area for non-critical paths. After placement, the place+routetool will attempt to route the design while minimizing w ire delay. Place+route tools often includeadditional facilities for clock tree synthesis, power routing, and block level floorplanning. Figure 1shows how Encounter fits into the 6.375 toolflow.The following documentation is lo cated in the course locker (/mit/6.375/doc) and provides addi-tional information about Encounter and the Tower 0.18 µm Standard Cell Library.• tsl-180nm-sc-databook.pdf - Databook for Tower 0.18 µm Standard Cell Library• encounter-user-guide.pdf - Encounter user guide• encounter-command-line-ref.pdf - Encounter text command reference• encounter-menu-ref.pdf - Encounter GUI referenceGetting startedBefore using the 6.375 toolflow you must add the course locker and run the course setup script withthe following two commands.% add 6.375% source /mit/6.375/setup.cshFor this tutorial we will be using an unpipelined SMIPSv1 processor as our example RTL design.You should create a working directory and checkout the SMIPSv1 example p roject from the courseCVS repository using the following commands.% mkdir tut5% cd tut5% cvs checkout examples/smipsv1-1stage-v% cd examples/smipsv1-1stage-vBefore starting, take a look at the subdirectories in the smips1-1stage-v project directory. Figure 2shows the system diagram which is implemented by the example cod e. When pushing designsthrough th e physical toolflow we will often refer to the core. The core m od ule contains everythingwhich will be on-chip, while blocks outside the core are assum e to be off-chip. For this tutorialwe are assuming that the processor and a combinational memory are located within the core. Acombinational memory means that the r ead address is specified at the beginning of the cycle, and6.375 Tutorial 5, Spring 2007 2TimingAreaVerilogSourceEncounter (FP) Design CompilerFloorPlanGateLevelNetlistTimingAreaLayoutGateLevelNetlistEncounter (PAR)StdCellLibDesign VisionFigure 1: Encounter Toolflowrd0rd1RegFile>> 2SignExtendir[15:0]RegFileDataMemvalrwCmpeq?Instruction Memvalpc+4branch+4DecoderControlSignalstohosttohost_entestrig_tohostir[25:21]ir[20:16]Addwdataaddrrdatarf_wenwb_selir[20:16]PCpc_selFigure 2: Block diagram for Unpipelined SMIPSv1 Processor6.375 Tutorial 5, Spring 2007 3the read data returns during the same cycle. Building large combinational memories is relativelyinefficient. It is much more common to use synchronous memories. A synchronous memory meansthat the read address is specified at the end of a cycle, and the r ead data returns during thenext cycle. From Figure 2 it should be clear that the unpipelined SMIPSv1 processor requirescombinational memories (or else it would turn into a four stage pipeline). For this tutorial we willnot be using a r eal combinational memory, but instead we will use a dummy memory to emulatethe combinational delay through the memory. Examine the source code in src and comparesmipsCorertl with smipsCore synth. The smipsCore rtl module is used for simulating theRTL of the SMIPSv1 processor and it includes a f unctional model for a large on-chip combinationalmemory. The smipsCore synth module is used for synthesizing the SMIPSv1 processor and it usesa dummy memory. The dummy memory combinationally connects the memory request bus tothe memory r esponse bus with a series of standard-cell buffers. Obviously, this is not fu nctionallycorrect, but it will help us illustrate more reasonable critical paths in the design. In later tutorials,we will start using memory generators which will create synchronous on-chip SRAMs.Now examine the build directory. This directory will contain all generated content includingsimulators, synthesized gate-level Verilog, and final layout. In this course we will always try to keepgenerated content separate from our source RTL. This keeps our project directories well organized,and helps prevent us from un intentionally modifying our source RTL. There are subdirectories inthe build directory for each major step in the 6.375 toolflow. These subdirectories contain scriptsand configuration files for running the tools required for that step in the to olflow. For this tutorialwe will work in the enc-par directory for place+route and in the enc-fp directory for floorplanning.Since Encounter takes a gate-level netlist as input, we need to run Synopsys Design Compiler tosynthesize this netlist from the RTL. The following commands will run Design Compiler. ConsultTutorial 4: RTL-to-Gates Synthesis using Synopsys Design Compiler for more information.% pwdtut5/examples/smipsv1-1stage-v% cd build/dc-synth% makeAutomatically Placing and Routing the ProcessorWe w ill begin by running several Encounter commands manually before learning how we can au-tomate the tools with scripts. Encounter can generate a large number of output files, so we will berunnin g Encounter within a build directory beneath enc-par. Before actually using Encounter toperform place+route, we need to u niquify our netlist. A u nique netlist is one in which the modulehierarchy is a true tree; in other words every module is instantiated once and only once. Use thefollowing commands to create a build directory and to uniquify the synthesized netlist.% pwdtut5/examples/smipsv1-1stage-v/build% cd enc-par% mkdir build% cd build% uniquifyNetlist -top smipsCore_synth synthesized_unique.v \../../dc-synth/current/synthesized.v6.375 Tutorial 5, Spring 2007 4When this is finished the uniqu ified netlist is called synthesizedunique.v, and it will be in yourEncounter build directory. We can now start the Encounter GUI. Later we will see how to runencounter without the GUI for scripting purposes. The following command starts Encounter andleaves you at the Encounter command p rompt. We


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MIT 6 375 - Automatic Placement and Routing using Cadence Encounter

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